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== Overview ==
 
== Overview ==
 
Positioned as a replacement for the {{\\|845}} for always-connected [[ARM]]-based PCs and fabricated on Samsung's second-generation [[10 nm process|10LPP process]], the 850 is for the most part a higher-binned version of its predecessor. The chip features four high-performance cores based on the {{armh|Cortex-A75|l=arch}} microarchitecture and six low-power cores based on the {{armh|Cortex-A55|l=arch}} microarchitecture. This chip incorporates the X20 LTE modem, supporting Cat 18 up to 1.2 Gbps download and Cat 13 up to 150 Mbps upload.
 
Positioned as a replacement for the {{\\|845}} for always-connected [[ARM]]-based PCs and fabricated on Samsung's second-generation [[10 nm process|10LPP process]], the 850 is for the most part a higher-binned version of its predecessor. The chip features four high-performance cores based on the {{armh|Cortex-A75|l=arch}} microarchitecture and six low-power cores based on the {{armh|Cortex-A55|l=arch}} microarchitecture. This chip incorporates the X20 LTE modem, supporting Cat 18 up to 1.2 Gbps download and Cat 13 up to 150 Mbps upload.
 +
 +
== Cache ==
 +
{{main|arm_holdings/microarchitectures/cortex-a75#Memory_Hierarchy|arm_holdings/microarchitectures/cortex-a55#Memory_Hierarchy|l1=Cortex-A75 § Cache|l2=Cortex-A55 § Cache}}
 +
 +
Quad-core cluster {{armh|Cortex-A75|l=arch}}:
 +
{{cache size
 +
|l1 cache=512 KiB
 +
|l1i cache=256 KiB
 +
|l1i break=4x64 KiB
 +
|l1i desc=4-way set associative
 +
|l1d cache=256 KiB
 +
|l1d break=4x64 KiB
 +
|l1d desc=4-way set associative
 +
|l2 cache=1 MiB
 +
|l2 break=4x256 KiB
 +
|l2 desc=8-way set associative
 +
}}
 +
 +
Quad-core cluster {{armh|Cortex-A55|l=arch}}:
 +
{{cache size
 +
|l1 cache=512 KiB
 +
|l1i cache=256 KiB
 +
|l1i break=4x64 KiB
 +
|l1i desc=2-way set associative
 +
|l1d cache=256 KiB
 +
|l1d break=4x64 KiB
 +
|l1d desc=4-way set associative
 +
|l2 cache=512 KiB
 +
|l2 break=4x128 KiB
 +
|l2 desc=8-way set associative
 +
}}
 +
 +
* 2 MiB L3
  
 
== Memory controller ==
 
== Memory controller ==

Revision as of 23:11, 16 June 2019

Edit Values
Snapdragon 850
General Info
DesignerQualcomm
ManufacturerSamsung
Model NumberSDM850
MarketMobile
IntroductionJune 5, 2018 (announced)
June 5, 2018 (launched)
General Specs
FamilySnapdragon 800
Frequency2,960 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A75, Cortex-A55
Core NameKryo 385 Gold, Kryo 385 Silver
Process10 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads8
Max Memory8 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)

Snapdragon 850 is a high-performance 64-bit ARM LTE system on a chip designed by Qualcomm and introduced in mid-2018. Fabricated on Samsung's 10nm LPP process, the 850 features four Kryo 385 Silver high-efficiency cores operating at ? GHz along with two high-performance Kryo 385 Gold operating at 2.96 GHz. The Snapdragon 850 integrates the Adreno 630 GPU operation at ? MHz and features an X20 LTE modem supporting Cat 13 uplink and Cat 18 downlink. This chip supports up to 8 GiB of quad-channel LPDDR4X-3733 memory.

Overview

Positioned as a replacement for the 845 for always-connected ARM-based PCs and fabricated on Samsung's second-generation 10LPP process, the 850 is for the most part a higher-binned version of its predecessor. The chip features four high-performance cores based on the Cortex-A75 microarchitecture and six low-power cores based on the Cortex-A55 microarchitecture. This chip incorporates the X20 LTE modem, supporting Cat 18 up to 1.2 Gbps download and Cat 13 up to 150 Mbps upload.

Cache

Main articles: Cortex-A75 § Cache and Cortex-A55 § Cache


Quad-core cluster Cortex-A75:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
4x64 KiB4-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
4x64 KiB4-way set associative 
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB8-way set associative 

Quad-core cluster Cortex-A55:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
4x64 KiB2-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
4x64 KiB4-way set associative 
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  4x128 KiB8-way set associative 
  • 2 MiB L3

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-3733
Supports ECCNo
Max Mem8 GiB
Frequency1866 MHz
Controllers1
Channels4
Width16 bit
Max Bandwidth29.87 GiB/s
30,586.88 MiB/s
32.073 GB/s
32,072.668 MB/s
0.0292 TiB/s
0.0321 TB/s
Bandwidth
Single 6.95 GiB/s
Double 13.91 GiB/s
Quad 29.87 GiB/s

DSP

This chip features Qualcomm's Hexagon 685 DSP.

Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUAdreno 630
DesignerQualcomm
Frequency? MHz
"? MHz" is not a number.
Standards
DirectX12
OpenCL2.0
OpenGL ES3.2
Vulkan1.0
  • Hardware Acceleration
  • 4K HDR video playback (10-bit color depth, Rec. 2020 color gamut)
  • Decode: H.264 (AVC), H.265 (HEVC) and VP9
  • Up to 4K Ultra HD video capture @ 30FPS
  • Up to 1080p video capture @120 FPS

Audio

  • Aqstic audio codec and Aqstic smart speaker amplifier
    • Up to native DSD support, PCM up to 384 kHz/32-bit
  • Qualcomm aptX audio playback with support for aptX Classic and HD

ISP

  • 2x Image Sensor Processor (ISP)
  • 14-bit

Megapixel:

  • Up to 16 MP dual camera
  • Up to 32 MP single camera

Connectivity

  • WiFi
    • Integrated 802.11ac 2 x 2 with MU-MIMO
    • Tri-band Wi-Fi: 2.4 GHz and 5 GHz with Dual
    • Band Simultaneous (DBS) + 60 GHz
  • Bluetooth 5.0
  • RF Front End
  • LTE Modem
    • Snapdragon X15
      • Downlink:
        • Category 18 up to 1,200 Mbps
        • 5 x 20 MHz carrier aggregation, up to 256-QAM
        • Up to 4 x 4 MIMO on three aggregated carriers
      • Uplink:
        • Category 13 up to 150 Mbps
        • 2 x 20 MHz carrier aggregation, up to 64-QAM

Location

  • GPS
    • Glonass, BeiDou, Galileo, QZSS, and SBAS
  • Low power geofencing and tracking, sensor assisted navigation
Retrieved from "https://en.wikichip.org/w/index.php?title=qualcomm/snapdragon_800/850&oldid=92029"
Facts about "Snapdragon 850 - Qualcomm"
RDF feed
base frequency2,960 MHz (2.96 GHz, 2,960,000 kHz) +
core count8 +
core nameKryo 385 Gold + and Kryo 385 Silver +
designerQualcomm +
dspHexagon 685 DSP +
familySnapdragon 800 +
first announcedJune 5, 2018 +
first launchedJune 5, 2018 +
full page namequalcomm/snapdragon 800/850 +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuAdreno 630 +
integrated gpu designerQualcomm +
isaARMv8 +
isa familyARM +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description4-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description4-way set associative + and 2-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + and 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
ldateJune 5, 2018 +
manufacturerSamsung +
market segmentMobile +
max cpu count1 +
max memory8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) +
max memory bandwidth29.87 GiB/s (30,586.88 MiB/s, 32.073 GB/s, 32,072.668 MB/s, 0.0292 TiB/s, 0.0321 TB/s) +
max memory channels4 +
microarchitectureCortex-A75 + and Cortex-A55 +
model numberSDM850 +
nameSnapdragon 850 +
process10 nm (0.01 μm, 1.0e-5 mm) +
smp max ways1 +
supported memory typeLPDDR4X-3733 +
technologyCMOS +
thread count8 +
word size64 bit (8 octets, 16 nibbles) +