From WikiChip
Difference between revisions of "intel/xeon gold/5222"
| (11 intermediate revisions by the same user not shown) | |||
| Line 2: | Line 2: | ||
{{chip | {{chip | ||
|name=Xeon Gold 5222 | |name=Xeon Gold 5222 | ||
| − | |image= | + | |image=cascade lake sp (front).png |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=5222 | |model number=5222 | ||
| + | |part number=CD8069504193501 | ||
| + | |s-spec=SRF8V | ||
|market=Server | |market=Server | ||
| − | |first announced= | + | |first announced=April 2, 2019 |
| − | |first launched= | + | |first launched=April 2, 2019 |
| + | |release price (tray)=$1,221.00 | ||
|family=Xeon Gold | |family=Xeon Gold | ||
| − | |series= | + | |series=5200 |
|locked=Yes | |locked=Yes | ||
|frequency=3,800 MHz | |frequency=3,800 MHz | ||
|turbo frequency1=3,900 MHz | |turbo frequency1=3,900 MHz | ||
| + | |bus type=DMI 3.0 | ||
| + | |bus links=4 | ||
| + | |bus rate=8 GT/s | ||
|clock multiplier=38 | |clock multiplier=38 | ||
| − | |cpuid= | + | |cpuid=0x50655 |
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
| Line 23: | Line 29: | ||
|core name=Cascade Lake SP | |core name=Cascade Lake SP | ||
|core family=6 | |core family=6 | ||
| − | |core stepping= | + | |core stepping=B1 |
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
| Line 30: | Line 36: | ||
|thread count=8 | |thread count=8 | ||
|max cpus=4 | |max cpus=4 | ||
| − | |max memory= | + | |max memory=1 TiB |
|tdp=105 W | |tdp=105 W | ||
|tcase min=0 °C | |tcase min=0 °C | ||
| Line 36: | Line 42: | ||
|dts min=0 °C | |dts min=0 °C | ||
|dts max=104 °C | |dts max=104 °C | ||
| − | |package | + | |package name 1=intel,fclga_3647 |
| + | |predecessor=Xeon Gold 5122 | ||
| + | |predecessor link=intel/xeon_gold/5122 | ||
}} | }} | ||
| − | '''Xeon Gold 5222''' is a {{arch|64}} [[quad-core]] [[x86]] | + | '''Xeon Gold 5222''' is a {{arch|64}} [[quad-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 5222 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports two {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.8 GHz with a TDP of 105 W and features a {{intel|turbo boost}} frequency of up to 3.9 GHz. |
| + | |||
| + | Note that this is the only processor in the {{intel|Xeon Gold}} 52xx series with two 512b [[FMA]] units. | ||
== Cache == | == Cache == | ||
| Line 66: | Line 76: | ||
|type=DDR4-2933 | |type=DDR4-2933 | ||
|ecc=Yes | |ecc=Yes | ||
| − | |max mem= | + | |max mem=1 TiB |
|controllers=2 | |controllers=2 | ||
|channels=6 | |channels=6 | ||
| − | |max bandwidth= | + | |max bandwidth=131.13 GiB/s |
| − | |bandwidth schan= | + | |bandwidth schan=21.86 GiB/s |
| − | |bandwidth dchan= | + | |bandwidth dchan=43.71 GiB/s |
| − | |bandwidth qchan= | + | |bandwidth qchan=87.42 GiB/s |
| − | |bandwidth hchan= | + | |bandwidth hchan=131.13 GiB/s |
}} | }} | ||
== Expansions == | == Expansions == | ||
| − | {{expansions | + | {{expansions main |
| − | | pcie revision | + | | |
| − | | pcie lanes | + | {{expansions entry |
| − | | pcie config | + | |type=PCIe |
| − | | pcie config 2 | + | |pcie revision=3.0 |
| − | | pcie config 3 | + | |pcie lanes=48 |
| + | |pcie config=1x16 | ||
| + | |pcie config 2=x8 | ||
| + | |pcie config 3=x4 | ||
| + | }} | ||
}} | }} | ||
| Line 116: | Line 130: | ||
|avx512vbmi=No | |avx512vbmi=No | ||
|avx5124fmaps=No | |avx5124fmaps=No | ||
| − | |avx512vnni= | + | |avx512vnni=Yes |
|avx5124vnniw=No | |avx5124vnniw=No | ||
|avx512vpopcntdq=No | |avx512vpopcntdq=No | ||
| Line 160: | Line 174: | ||
|vpro=Yes | |vpro=Yes | ||
|vtx=Yes | |vtx=Yes | ||
| − | |vtd= | + | |vtd=Yes |
|ept=Yes | |ept=Yes | ||
|mpx=No | |mpx=No | ||
| Line 167: | Line 181: | ||
|osguard=No | |osguard=No | ||
|intqat=No | |intqat=No | ||
| − | |dlboost= | + | |dlboost=Yes |
|3dnow=No | |3dnow=No | ||
|e3dnow=No | |e3dnow=No | ||
| Line 186: | Line 200: | ||
|amdpb2=No | |amdpb2=No | ||
|amdpbod=No | |amdpbod=No | ||
| + | }} | ||
| + | |||
| + | == Frequencies == | ||
| + | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
| + | {{frequency table | ||
| + | |freq_base=3,800MHz | ||
| + | |freq_1=3,900MHz | ||
| + | |freq_2=3,900MHz | ||
| + | |freq_3=3,900MHz | ||
| + | |freq_4=3,900MHz | ||
| + | |freq_avx2_base=3,300MHz | ||
| + | |freq_avx2_1=3,800MHz | ||
| + | |freq_avx2_2=3,800MHz | ||
| + | |freq_avx2_3=3,800MHz | ||
| + | |freq_avx2_4=3,800MHz | ||
| + | |freq_avx512_base=2,700MHz | ||
| + | |freq_avx512_1=3,700MHz | ||
| + | |freq_avx512_2=3,700MHz | ||
| + | |freq_avx512_3=3,500MHz | ||
| + | |freq_avx512_4=3,500MHz | ||
}} | }} | ||
Latest revision as of 23:53, 23 May 2019
| Edit Values | |
| Xeon Gold 5222 | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Model Number | 5222 |
| Part Number | CD8069504193501 |
| S-Spec | SRF8V |
| Market | Server |
| Introduction | April 2, 2019 (announced) April 2, 2019 (launched) |
| Release Price | $1,221.00 (tray) |
| Shop | Amazon |
| General Specs | |
| Family | Xeon Gold |
| Series | 5200 |
| Locked | Yes |
| Frequency | 3,800 MHz |
| Turbo Frequency | 3,900 MHz (1 core) |
| Bus type | DMI 3.0 |
| Bus rate | 4 × 8 GT/s |
| Clock multiplier | 38 |
| CPUID | 0x50655 |
| Microarchitecture | |
| ISA | x86-64 (x86) |
| Microarchitecture | Cascade Lake |
| Platform | Purley |
| Chipset | Lewisburg |
| Core Name | Cascade Lake SP |
| Core Family | 6 |
| Core Stepping | B1 |
| Process | 14 nm |
| Technology | CMOS |
| Word Size | 64 bit |
| Cores | 4 |
| Threads | 8 |
| Max Memory | 1 TiB |
| Multiprocessing | |
| Max SMP | 4-Way (Multiprocessor) |
| Electrical | |
| TDP | 105 W |
| Tcase | 0 °C – 71 °C |
| TDTS | 0 °C – 104 °C |
| Packaging | |
| Package | FCLGA-3647 (FCLGA) |
| Dimension | 76.16 mm × 56.6 mm |
| Pitch | 0.8585 mm × 0.9906 mm |
| Contacts | 3647 |
| Socket | Socket P, LGA-3647 |
| Succession | |
Xeon Gold 5222 is a 64-bit quad-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 5222 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports two AVX-512 FMA units as well as two UPI links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.8 GHz with a TDP of 105 W and features a turbo boost frequency of up to 3.9 GHz.
Note that this is the only processor in the Xeon Gold 52xx series with two 512b FMA units.
Cache[edit]
- Main article: Skylake § Cache
The Xeon Gold 5222 features a considerably larger non-default 16.5 MiB of L3, a size that would normally be found on a 12-core part.
|
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
|||||||||||||||||||||||||||||||||||||
Memory controller[edit]
|
Integrated Memory Controller
|
||||||||||||||
|
||||||||||||||
Expansions[edit]
Expansion Options |
|||||
|
|||||
Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
| Mode | Base | Turbo Frequency/Active Cores | |||
|---|---|---|---|---|---|
| 1 | 2 | 3 | 4 | ||
| Normal | 3,800MHz | 3,900MHz | 3,900MHz | 3,900MHz | 3,900MHz |
| AVX2 | 3,300MHz | 3,800MHz | 3,800MHz | 3,800MHz | 3,800MHz |
| AVX512 | 2,700MHz | 3,700MHz | 3,700MHz | 3,500MHz | 3,500MHz |
Facts about "Xeon Gold 5222 - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 5222 - Intel#pcie + |
| base frequency | 3,800 MHz (3.8 GHz, 3,800,000 kHz) + |
| bus links | 4 + |
| bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
| bus type | DMI 3.0 + |
| chipset | Lewisburg + |
| clock multiplier | 38 + |
| core count | 4 + |
| core family | 6 + |
| core name | Cascade Lake SP + |
| core stepping | B1 + |
| cpuid | 0x50655 + |
| designer | Intel + |
| family | Xeon Gold + |
| first announced | April 2, 2019 + |
| first launched | April 2, 2019 + |
| full page name | intel/xeon gold/5222 + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has advanced vector extensions 512 | true + |
| has ecc memory support | true + |
| has extended page tables support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost + |
| has intel deep learning boost | true + |
| has intel enhanced speedstep technology | true + |
| has intel speed shift technology | true + |
| has intel trusted execution technology | true + |
| has intel turbo boost technology 2 0 | true + |
| has intel vpro technology | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has locked clock multiplier | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has transactional synchronization extensions | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| instance of | microprocessor + |
| isa | x86-64 + |
| isa family | x86 + |
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
| l3$ description | 11-way set associative + |
| l3$ size | 16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) + |
| ldate | April 2, 2019 + |
| main image | |
| manufacturer | Intel + |
| market segment | Server + |
| max case temperature | 344.15 K (71 °C, 159.8 °F, 619.47 °R) + |
| max cpu count | 4 + |
| max dts temperature | 104 °C + |
| max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
| max memory bandwidth | 131.13 GiB/s (134,277.12 MiB/s, 140.8 GB/s, 140,799.765 MB/s, 0.128 TiB/s, 0.141 TB/s) + |
| max memory channels | 6 + |
| microarchitecture | Cascade Lake + |
| min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
| min dts temperature | 0 °C + |
| model number | 5222 + |
| name | Xeon Gold 5222 + |
| number of avx-512 execution units | 2 + |
| package | FCLGA-3647 + |
| part number | CD8069504193501 + |
| platform | Purley + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
| release price | $ 1,221.00 (€ 1,098.90, £ 989.01, ¥ 126,165.93) + |
| release price (tray) | $ 1,221.00 (€ 1,098.90, £ 989.01, ¥ 126,165.93) + |
| s-spec | SRF8V + |
| series | 5200 + |
| smp max ways | 4 + |
| socket | Socket P + and LGA-3647 + |
| supported memory type | DDR4-2933 + |
| tdp | 105 W (105,000 mW, 0.141 hp, 0.105 kW) + |
| technology | CMOS + |
| thread count | 8 + |
| turbo frequency (1 core) | 3,900 MHz (3.9 GHz, 3,900,000 kHz) + |
| word size | 64 bit (8 octets, 16 nibbles) + |