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Difference between revisions of "intel/xeon gold/6252"
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== Cache == | == Cache == | ||
{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}} | {{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}} | ||
− | The Xeon | + | The Xeon Gold 6252 features a larger non-default 35.75 MiB of [[L3]], a size that would normally be found on a 26-core part. |
{{cache size | {{cache size | ||
|l1 cache=1.5 MiB | |l1 cache=1.5 MiB |
Revision as of 21:28, 7 May 2019
Edit Values | |
General Info | |
Microarchitecture |
Xeon Gold 6252 is a 64-bit 24-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6252 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.1 GHz with a TDP of 150 W and features a turbo boost frequency of up to 3.7 GHz.
Cache
- Main article: Cascade Lake § Cache
The Xeon Gold 6252 features a larger non-default 35.75 MiB of L3, a size that would normally be found on a 26-core part.
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Xeon Gold 6252 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 6252 - Intel#pcie + |
base frequency | 2,100 MHz (2.1 GHz, 2,100,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
chipset | Lewisburg + |
clock multiplier | 21 + |
core count | 24 + |
core family | 6 + |
core model | 85 + |
core name | Cascade Lake SP + |
core stepping | B0 + |
designer | Intel + |
family | Xeon Gold + |
first announced | April 2, 2019 + |
first launched | April 2, 2019 + |
full page name | intel/xeon gold/6252 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost + |
has intel deep learning boost | true + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 35.75 MiB (36,608 KiB, 37,486,592 B, 0.0349 GiB) + |
ldate | April 2, 2019 + |
main image | + |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 359.15 K (86 °C, 186.8 °F, 646.47 °R) + |
max cpu count | 4 + |
max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
max memory bandwidth | 131.13 GiB/s (134,277.12 MiB/s, 140.8 GB/s, 140,799.765 MB/s, 0.128 TiB/s, 0.141 TB/s) + |
max memory channels | 6 + |
microarchitecture | Cascade Lake + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | 6252 + |
name | Xeon Gold 6252 + |
package | FCLGA-3647 + |
part number | CD8069504194401 + and BX806956252 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 3,655.00 (€ 3,289.50, £ 2,960.55, ¥ 377,671.15) + and $ 3,662.00 (€ 3,295.80, £ 2,966.22, ¥ 378,394.46) + |
release price (box) | $ 3,662.00 (€ 3,295.80, £ 2,966.22, ¥ 378,394.46) + |
release price (tray) | $ 3,655.00 (€ 3,289.50, £ 2,960.55, ¥ 377,671.15) + |
s-spec | SRF91 + |
s-spec (qs) | QRAL + |
series | 6200 + |
smp interconnect | UPI + |
smp interconnect links | 3 + |
smp interconnect rate | 10.4 GT/s + |
smp max ways | 4 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2933 + |
tdp | 150 W (150,000 mW, 0.201 hp, 0.15 kW) + |
technology | CMOS + |
thread count | 48 + |
turbo frequency (1 core) | 3,700 MHz (3.7 GHz, 3,700,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |