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Difference between revisions of "intel/xeon gold/5218n"
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|l3 desc=11-way set associative
 
|l3 desc=11-way set associative
 
|l3 policy=write-back
 
|l3 policy=write-back
 +
}}
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== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2666
 +
|ecc=Yes
 +
|max mem=1 TiB
 +
|controllers=2
 +
|channels=6
 +
|max bandwidth=119.21 GiB/s
 +
|bandwidth schan=19.87 GiB/s
 +
|bandwidth dchan=39.74 GiB/s
 +
|bandwidth qchan=79.47 GiB/s
 +
|bandwidth hchan=119.21 GiB/s
 
}}
 
}}

Revision as of 00:57, 4 April 2019

Edit Values
Xeon Gold 5218N
cascade lake sp (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Number5218N
Part NumberCD8069504289900
S-SpecSRFD9
MarketServer
IntroductionApril 2, 2019 (announced)
April 2, 2019 (launched)
Release Price$1,375.00 (tray)
ShopAmazon
General Specs
FamilyXeon Gold
Series5200
LockedYes
Frequency2,300 MHz
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier23
CPUID0x50655
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Core NameCascade Lake SP
Core Family6
Core SteppingL1
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores16
Threads32
Max Memory1 TiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
Electrical
TDP105 W
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647

Xeon Gold 5218N is a 64-bit 16-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 5218N is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports one AVX-512 FMA units as well as three UPI links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2666 memory, operates at 2.3 GHz with a TDP of 105 W and features a turbo boost frequency of up to 3.7 GHz.


Cache

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1 MiB
1,024 KiB
1,048,576 B
L1I$512 KiB
524,288 B
0.5 MiB
16x32 KiB8-way set associative 
L1D$512 KiB
524,288 B
0.5 MiB
16x32 KiB8-way set associativewrite-back
L2$16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
  16x1 MiB16-way set associativewrite-back
L3$22 MiB
22,528 KiB
23,068,672 B
0.0215 GiB
  16x1.375 MiB11-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem1 TiB
Controllers2
Channels6
Max Bandwidth119.21 GiB/s
122,071.04 MiB/s
128.001 GB/s
128,000.763 MB/s
0.116 TiB/s
0.128 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_gold/5218n&oldid=87955"
Facts about "Xeon Gold 5218N - Intel"
RDF feed
base frequency2,300 MHz (2.3 GHz, 2,300,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
chipsetLewisburg +
clock multiplier23 +
core count16 +
core family6 +
core nameCascade Lake SP +
core steppingL1 +
cpuid0x50655 +
designerIntel +
familyXeon Gold +
first announcedApril 2, 2019 +
first launchedApril 2, 2019 +
full page nameintel/xeon gold/5218n +
has ecc memory supporttrue +
has locked clock multipliertrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size1,024 KiB (1,048,576 B, 1 MiB) +
l1d$ description8-way set associative +
l1d$ size512 KiB (524,288 B, 0.5 MiB) +
l1i$ description8-way set associative +
l1i$ size512 KiB (524,288 B, 0.5 MiB) +
l2$ description16-way set associative +
l2$ size16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
l3$ description11-way set associative +
l3$ size22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) +
ldateApril 2, 2019 +
main imageFile:cascade lake sp (front).png +
manufacturerIntel +
market segmentServer +
max cpu count4 +
max memory1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
microarchitectureCascade Lake +
model number5218N +
nameXeon Gold 5218N +
packageFCLGA-3647 +
part numberCD8069504289900 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 1,375.00 (€ 1,237.50, £ 1,113.75, ¥ 142,078.75) +
release price (tray)$ 1,375.00 (€ 1,237.50, £ 1,113.75, ¥ 142,078.75) +
s-specSRFD9 +
series5200 +
smp max ways4 +
socketSocket P + and LGA-3647 +
supported memory typeDDR4-2666 +
tdp105 W (105,000 mW, 0.141 hp, 0.105 kW) +
technologyCMOS +
thread count32 +
word size64 bit (8 octets, 16 nibbles) +