Difference between revisions of "intel/xeon gold/5222"

	Edit Values
	Xeon Gold 5222
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	5222
Part Number	CD8069504193501
S-Spec	SRF8V
Market	Server
Introduction	April 2, 2019 (announced); April 2, 2019 (launched)
Release Price	$1,221.00 (tray)
Shop	Amazon
	General Specs
Family	Xeon Gold
Series	5200
Locked	Yes
Frequency	3,800 MHz
Turbo Frequency	3,900 MHz (1 core)
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	38
CPUID	0x50655
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Cascade Lake
Platform	Purley
Chipset	Lewisburg
Core Name	Cascade Lake SP
Core Family	6
Core Stepping	B1
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	4
Threads	8
Max Memory	1 TiB
	Multiprocessing
Max SMP	4-Way (Multiprocessor)
	Electrical
TDP	105 W
Tcase	0 °C – 71 °C
TDTS	0 °C – 104 °C
	Packaging
Package	FCLGA-3647 (FCLGA)
Dimension	76.16 mm × 56.6 mm
Pitch	0.8585 mm × 0.9906 mm
Contacts	3647
Socket	Socket P, LGA-3647

Revision as of 00:22, 4 April 2019

Xeon Gold 5222 is a 64-bit quad-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 5222 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports one AVX-512 FMA units as well as three UPI links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.8 GHz with a TDP of 105 W and features a turbo boost frequency of up to 3.9 GHz.

Cache

Main article: Skylake § Cache

The Xeon Gold 5222 features a considerably larger non-default 16.5 MiB of L3, a size that would normally be found on a 12-core part.

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

256 KiB

262,144 B
0.25 MiB

L1I$	128 KiB 131,072 B 0.125 MiB	4x32 KiB	8-way set associative
L1D$	128 KiB 131,072 B 0.125 MiB	4x32 KiB	8-way set associative	write-back

L2$

4 MiB

4,096 KiB
4,194,304 B
0.00391 GiB

		4x1 MiB	16-way set associative	write-back

L3$

16.5 MiB

16,896 KiB
17,301,504 B
0.0161 GiB

		12x1.375 MiB	11-way set associative	write-back

Memory controller

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2933
Supports ECC	Yes
Max Mem	768 GiB
Controllers	2
Channels	6
Max Bandwidth	119.21 GiB/s 122,071.04 MiB/s 128.001 GB/s 128,000.763 MB/s 0.116 TiB/s 0.128 TB/s
Bandwidth	Single 19.87 GiB/s Double 39.74 GiB/s Quad 79.47 GiB/s Hexa 119.21 GiB/s

Expansions

[Edit/Modify Expansions Info]

Expansion Options

PCIe

Revision	3.0
Max Lanes	48
Configs	x16, x8, x4

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
AVX-512	Advanced Vector 512-bit (2 Units)
AVX512F	AVX-512 Foundation
AVX512CD	AVX-512 Conflict Detection
AVX512BW	AVX-512 Byte and Word
AVX512DQ	AVX-512 Doubleword and Quadword Instructions
AVX512VL	AVX-512 Vector Length
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
HT	Hyper-Threading
TBT 2.0	Turbo Boost Technology 2.0
EIST	Enhanced SpeedStep Technology
SST	Speed Shift Technology
TXT	Trusted Execution Technology (SMX)
vPro	Intel vPro
VT-x	VT-x (Virtualization)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions
VMD	Volume Management Device
NM	Node Manager
KPT	Key Protection Technology
PTT	Platform Trust Technology
MBE Ctrl	Mode-Based Execute Control

@@ Line 2: / Line 2: @@
 {{chip
 |name=Xeon Gold 5222
-|image=skylake sp (basic).png
+|image=cascade lake sp (front).png
 |designer=Intel
 |manufacturer=Intel
 |model number=5222
+|part number=CD8069504193501
+|s-spec=SRF8V
 |market=Server
-|first announced=March, 2019
+|first announced=April 2, 2019
-|first launched=March, 2019
+|first launched=April 2, 2019
+|release price (tray)=$1,221.00
 |family=Xeon Gold
-|series=5000
+|series=5200
 |locked=Yes
 |frequency=3,800 MHz
 |turbo frequency1=3,900 MHz
+|bus type=DMI 3.0
+|bus links=4
+|bus rate=8 GT/s
 |clock multiplier=38
-|cpuid=0x50654
+|cpuid=0x50655
 |isa=x86-64
 |isa family=x86
@@ Line 23: / Line 29: @@
 |core name=Cascade Lake SP
 |core family=6
-|core stepping=H0
+|core stepping=B1
 |process=14 nm
 |technology=CMOS
@@ Line 30: / Line 36: @@
 |thread count=8
 |max cpus=4
-|max memory=? GiB
+|max memory=1 TiB
 |tdp=105 W
 |tcase min=0 °C
@@ Line 36: / Line 42: @@
 |dts min=0 °C
 |dts max=104 °C
-|package module 1={{packages/intel/fclga-3647}}
+|package name 1=intel,fclga_3647
 }}
 '''Xeon Gold 5222''' is a {{arch|64}} [[quad-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 5222 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.8 GHz with a TDP of 105 W and features a {{intel|turbo boost}} frequency of up to 3.9 GHz.

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Gold 5222 - Intel#io +
base frequency	3,800 MHz (3.8 GHz, 3,800,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Lewisburg +
clock multiplier	38 +
core count	4 +
core family	6 +
core name	Cascade Lake SP +
core stepping	B1 +
cpuid	0x50655 +
designer	Intel +
family	Xeon Gold +
first announced	April 2, 2019 +
first launched	April 2, 2019 +
full page name	intel/xeon gold/5222 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	256 KiB (262,144 B, 0.25 MiB) +
l1d$ description	8-way set associative +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	8-way set associative +
l1i$ size	128 KiB (131,072 B, 0.125 MiB) +
l2$ description	16-way set associative +
l2$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ description	11-way set associative +
l3$ size	16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +
ldate	April 2, 2019 +
main image	+
manufacturer	Intel +
market segment	Server +
max case temperature	344.15 K (71 °C, 159.8 °F, 619.47 °R) +
max cpu count	4 +
max dts temperature	104 °C +
max memory	1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth	119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels	6 +
max pcie lanes	48 +
microarchitecture	Cascade Lake +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min dts temperature	0 °C +
model number	5222 +
name	Xeon Gold 5222 +
number of avx-512 execution units	2 +
package	FCLGA-3647 +
part number	CD8069504193501 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 1,221.00 (€ 1,098.90, £ 989.01, ¥ 126,165.93) +
release price (tray)	$ 1,221.00 (€ 1,098.90, £ 989.01, ¥ 126,165.93) +
s-spec	SRF8V +
series	5200 +
smp max ways	4 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2933 +
tdp	105 W (105,000 mW, 0.141 hp, 0.105 kW) +
technology	CMOS +
thread count	8 +
turbo frequency (1 core)	3,900 MHz (3.9 GHz, 3,900,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

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