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Difference between revisions of "intel/xeon silver/4216"
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{{chip | {{chip | ||
|name=Xeon Silver 4216 | |name=Xeon Silver 4216 | ||
− | |image= | + | |image=cascade lake sp (front).png |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=4216 | |model number=4216 | ||
+ | |part number=CD8069504213901 | ||
+ | |s-spec=SRFBB | ||
|market=Server | |market=Server | ||
− | |first announced= | + | |first announced=April 2, 2019 |
− | |first launched= | + | |first launched=April 2, 2019 |
+ | |release price (tray)=$1,002.00 | ||
+ | |release price (box)=$1,012.00 | ||
|family=Xeon Silver | |family=Xeon Silver | ||
− | |series= | + | |series=4200 |
|locked=Yes | |locked=Yes | ||
|frequency=2,100 MHz | |frequency=2,100 MHz | ||
Line 22: | Line 26: | ||
|core name=Cascade Lake SP | |core name=Cascade Lake SP | ||
|core family=6 | |core family=6 | ||
+ | |core stepping=L1 | ||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
Line 28: | Line 33: | ||
|thread count=32 | |thread count=32 | ||
|max cpus=2 | |max cpus=2 | ||
− | |tdp= | + | |tdp=100 W |
|tcase min=0 °C | |tcase min=0 °C | ||
− | |tcase max= | + | |tcase max=79 °C |
− | + | |package name 1=intel,fclga_3647 | |
− | |||
− | |package | ||
}} | }} | ||
'''Xeon Silver 4216''' is a {{arch|64}} [[16-core]] [[x86]] mid-range performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Silver 4216 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports dual-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 2.1 GHz with a TDP of 100 W and features a {{intel|turbo boost}} frequency of up to 3.2 GHz. | '''Xeon Silver 4216''' is a {{arch|64}} [[16-core]] [[x86]] mid-range performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Silver 4216 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports dual-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 2.1 GHz with a TDP of 100 W and features a {{intel|turbo boost}} frequency of up to 3.2 GHz. |
Revision as of 18:53, 3 April 2019
Edit Values | |
Xeon Silver 4216 | |
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General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 4216 |
Part Number | CD8069504213901 |
S-Spec | SRFBB |
Market | Server |
Introduction | April 2, 2019 (announced) April 2, 2019 (launched) |
Release Price | $1,002.00 (tray) $1,012.00 (box) |
Shop | Amazon |
General Specs | |
Family | Xeon Silver |
Series | 4200 |
Locked | Yes |
Frequency | 2,100 MHz |
Turbo Frequency | 3,200 MHz (1 core) |
Clock multiplier | 21 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Cascade Lake SP |
Core Family | 6 |
Core Stepping | L1 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 16 |
Threads | 32 |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Electrical | |
TDP | 100 W |
Tcase | 0 °C – 79 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Xeon Silver 4216 is a 64-bit 16-core x86 mid-range performance server microprocessor introduced by Intel in early 2019. The Silver 4216 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports dual-way multiprocessing, sports one AVX-512 FMA units as well as two UPI links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 2.1 GHz with a TDP of 100 W and features a turbo boost frequency of up to 3.2 GHz.
Contents
Cache
- Main article: Cascade Lake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Features
[Edit/Modify Supported Features]
Facts about "Xeon Silver 4216 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Silver 4216 - Intel#io + |
base frequency | 2,100 MHz (2.1 GHz, 2,100,000 kHz) + |
chipset | Lewisburg + |
clock multiplier | 21 + |
core count | 16 + |
core family | 6 + |
core name | Cascade Lake SP + |
core stepping | L1 + |
designer | Intel + |
family | Xeon Silver + |
first announced | April 2, 2019 + |
first launched | April 2, 2019 + |
full page name | intel/xeon silver/4216 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) + |
ldate | April 2, 2019 + |
main image | ![]() |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 352.15 K (79 °C, 174.2 °F, 633.87 °R) + |
max cpu count | 2 + |
max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
microarchitecture | Cascade Lake + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | 4216 + |
name | Xeon Silver 4216 + |
package | FCLGA-3647 + |
part number | CD8069504213901 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 1,002.00 (€ 901.80, £ 811.62, ¥ 103,536.66) + and $ 1,012.00 (€ 910.80, £ 819.72, ¥ 104,569.96) + |
release price (box) | $ 1,012.00 (€ 910.80, £ 819.72, ¥ 104,569.96) + |
release price (tray) | $ 1,002.00 (€ 901.80, £ 811.62, ¥ 103,536.66) + |
s-spec | SRFBB + |
series | 4200 + |
smp max ways | 2 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2400 + |
tdp | 100 W (100,000 mW, 0.134 hp, 0.1 kW) + |
technology | CMOS + |
thread count | 32 + |
turbo frequency (1 core) | 3,200 MHz (3.2 GHz, 3,200,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |