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Difference between revisions of "intel/xeon platinum/9242"
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'''Xeon Platinum 9242''' is a [[48-core]] {{arch|64}} high-performance [[x86]] server microprocessor introduced by Intel in early [[2019]]. The 9242 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is fabricated on Intel's [[14 nm process]]. It operates at 2.3 GHz with a TDP of 350 W and a {{intel|turbo boost}} of up to 3.8 GHz. This processor supports up to twelve channels of DDR4-2933 memory. | '''Xeon Platinum 9242''' is a [[48-core]] {{arch|64}} high-performance [[x86]] server microprocessor introduced by Intel in early [[2019]]. The 9242 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is fabricated on Intel's [[14 nm process]]. It operates at 2.3 GHz with a TDP of 350 W and a {{intel|turbo boost}} of up to 3.8 GHz. This processor supports up to twelve channels of DDR4-2933 memory. | ||
+ | |||
+ | This processor cannot be purchased independently and is only sold as part of Intel's S9200WK Compute Module. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/cascade_lake#Memory_Hierarchy|l1=Cascade Lake § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=3 MiB | ||
+ | |l1i cache=1.5 MiB | ||
+ | |l1i break=48x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=1.5 MiB | ||
+ | |l1d break=48x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=48 MiB | ||
+ | |l2 break=48x1 MiB | ||
+ | |l2 desc=16-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=71.5 MiB | ||
+ | |l3 break=52x1.375 MiB | ||
+ | |l3 desc=11-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2933 | ||
+ | |ecc=Yes | ||
+ | |max mem=2 TiB | ||
+ | |controllers=4 | ||
+ | |channels=12 | ||
+ | |max bandwidth=262.26 GiB/s | ||
+ | |bandwidth schan=21.86 GiB/s | ||
+ | |bandwidth dchan=43.71 GiB/s | ||
+ | |bandwidth qchan=87.42 GiB/s | ||
+ | |bandwidth ochan=174.84 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions main | ||
+ | | | ||
+ | {{expansions entry | ||
+ | |type=PCIe | ||
+ | |pcie revision=3.0 | ||
+ | |pcie lanes=40 | ||
+ | |pcie config=1x16 | ||
+ | |pcie config 2=2x8 | ||
+ | |pcie config 3=1x8+2x4 | ||
+ | }} | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=No | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
+ | |avx512f=Yes | ||
+ | |avx512cd=Yes | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=Yes | ||
+ | |avx512dq=Yes | ||
+ | |avx512vl=Yes | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx512vnni=Yes | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |bfloat16=No | ||
+ | |tbt1=No | ||
+ | |tbt2=Yes | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |sst=Yes | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |ivmd=Yes | ||
+ | |intelnodecontroller=Yes | ||
+ | |intelnode=Yes | ||
+ | |kpt=Yes | ||
+ | |ptt=Yes | ||
+ | |intelrunsure=Yes | ||
+ | |mbe=Yes | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=Yes | ||
+ | |txt=Yes | ||
+ | |ht=Yes | ||
+ | |vpro=Yes | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |intqat=No | ||
+ | |dlboost=No | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
+ | |xfr2=No | ||
+ | |mxfr=No | ||
+ | |amdpb=No | ||
+ | |amdpb2=No | ||
+ | |amdpbod=No | ||
+ | }} |
Revision as of 14:20, 2 April 2019
Edit Values | |
Xeon Platinum 9242 | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 9242 |
Market | Server, HPC |
Introduction | April 2, 2019 (announced) April 2, 2019 (launched) |
Shop | Amazon |
General Specs | |
Family | Xeon Platinum |
Series | 9200 |
Locked | Yes |
Frequency | 2,300 MHz |
Turbo Frequency | 3,800 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 23 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Platform | Walker Pass |
Chipset | Lewisburg |
Core Name | Cascade Lake AP |
Core Family | 6 |
Process | 14 nm |
Technology | CMOS |
MCP | Yes (2 dies) |
Word Size | 64 bit |
Cores | 48 |
Threads | 96 |
Max Memory | 2 TiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Electrical | |
TDP | 350 W |
Packaging | |
Package | FCBGA-5903 (BGA) |
Pitch | 0.99 mm |
Contacts | 5903 |
Xeon Platinum 9242 is a 48-core 64-bit high-performance x86 server microprocessor introduced by Intel in early 2019. The 9242 is based on the Cascade Lake microarchitecture and is fabricated on Intel's 14 nm process. It operates at 2.3 GHz with a TDP of 350 W and a turbo boost of up to 3.8 GHz. This processor supports up to twelve channels of DDR4-2933 memory.
This processor cannot be purchased independently and is only sold as part of Intel's S9200WK Compute Module.
Contents
Cache
- Main article: Cascade Lake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options |
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Features
[Edit/Modify Supported Features]
Facts about "Xeon Platinum 9242 - Intel"
base frequency | 2,300 MHz (2.3 GHz, 2,300,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
chipset | Lewisburg + |
clock multiplier | 23 + |
core count | 48 + |
core family | 6 + |
core name | Cascade Lake AP + |
designer | Intel + |
die count | 2 + |
family | Xeon Platinum + |
first announced | April 2, 2019 + |
first launched | April 2, 2019 + |
full page name | intel/xeon platinum/9242 + |
has locked clock multiplier | true + |
instance of | microprocessor + |
is multi-chip package | true + |
isa | x86-64 + |
isa family | x86 + |
ldate | April 2, 2019 + |
main image | + |
manufacturer | Intel + |
market segment | Server + and HPC + |
max cpu count | 2 + |
max memory | 2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) + |
microarchitecture | Cascade Lake + |
model number | 9242 + |
name | Xeon Platinum 9242 + |
package | FCBGA-5903 + |
platform | Walker Pass + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
series | 9200 + |
smp max ways | 2 + |
tdp | 350 W (350,000 mW, 0.469 hp, 0.35 kW) + |
technology | CMOS + |
thread count | 96 + |
turbo frequency (1 core) | 3,800 MHz (3.8 GHz, 3,800,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |