Semiconductor & Computer Engineering
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Difference between revisions of "Template:multi-core processors info"
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| − | | style="text-align: center; background: #eeeedd; font-size: 16px;" colspan="2" | '''Multi-Core | + | | style="text-align: center; background: #eeeedd; font-size: 16px;" colspan="2" | '''Multi-Core CPUs''' |
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| + | |{{collist | ||
| + | | count = 4 | ||
| + | | no-list-type = yes | ||
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| − | + | * [[single-core|1]] | |
| − | + | * [[dual-core|2]] | |
| − | + | * [[tri-core|3]] | |
| − | + | * [[quad-core|4]] | |
| − | + | * [[penta-core|5]] | |
| − | + | * [[hexa-core|6]] | |
| − | + | * [[hepta-core|7]] | |
| − | + | * [[octa-core|8]] | |
| − | + | * [[nona-core|9]] | |
| − | + | * [[deca-core|10]] | |
| − | + | * [[undeca-core|11]] | |
| − | + | * [[dodeca-core|12]] | |
| − | + | * [[trideca-core|13]] | |
| − | + | * [[tetradeca-core|14]] | |
| − | + | * [[pentadeca-core|15]] | |
| − | + | * [[hexadeca-core|16]] | |
| − | + | * [[heptadeca-core|17]] | |
| − | + | * [[octadeca-core|18]] | |
| − | + | * [[nonadeca-core|19]] | |
| − | + | * [[icosa-core|20]] | |
| − | + | * [[henicosa-core|21]] | |
| − | + | * [[docosa-core|22]] | |
| − | + | * [[tricosa-core|23]] | |
| − | + | * [[tetracosa-core|24]] | |
| − | + | * [[pentacosa-core|25]] | |
| − | + | * [[hexacosa-core|26]] | |
| − | + | * [[heptacosa-core|27]] | |
| − | + | * [[octacosa-core|28]] | |
| − | + | * [[nonacosa-core|29]] | |
| − | + | * [[triaconta-core|30]] | |
| − | + | }} | |
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| − | | [[ | + | | colspan="2" style="text-align: center;" | [[Many-Core Microprocessor]] |
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| − | | | + | | colspan="2" style="text-align: center;" | [[chip_multiprocessor|Multi-Core Microprocessor]] |
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| − | | [[ | ||
|} | |} | ||
Latest revision as of 15:20, 26 March 2019
| Multi-Core CPUs | |
| Many-Core Microprocessor | |
| Multi-Core Microprocessor | |