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Difference between revisions of "arm holdings/microarchitectures/cortex-a9"
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(Key changes from {{\\|Cortex-A8}})
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=== Key changes from {{\\|Cortex-A8}} ===
 
=== Key changes from {{\\|Cortex-A8}} ===
 
* Fully synthesizable RTL (prior designs were hand/automated layout)
 
* Fully synthesizable RTL (prior designs were hand/automated layout)
 +
* [[40 nm process]] (from [[65 nm]])
 +
* New [[out-of-order]] pipeline (form [[in-order]])
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** Shorter pipeline (9-12 stages, down from 13)
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* 2x frequency (2 GHz, up from 1 GHz)
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* NEON
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** Added [[Half precision]] support
 +
{{expand list}}
  
 
== Licensees ==
 
== Licensees ==

Revision as of 23:22, 30 December 2018

Edit Values
Cortex-A9 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionOctober 3, 2007
Process40 nm
Succession

Cortex-A9 is the successor to the Cortex-A8, a low-power performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.

The Cortex-A9 was later succeeded by four independent lines - high-performance (A15), mainstream performance (A12), high efficiency (A7), and ultra-low power (A5).

Architecture

Key changes from Cortex-A8

This list is incomplete; you can help by expanding it.

Licensees

Arm named the following companies as licensees.

codenameCortex-A9 +
designerARM Holdings +
first launchedOctober 3, 2007 +
full page namearm holdings/microarchitectures/cortex-a9 +
instance ofmicroarchitecture +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A9 +
process40 nm (0.04 μm, 4.0e-5 mm) +