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Difference between revisions of "nec/microarchitectures/sx-aurora"
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{{nec title|SX-Aurora|arch}} | {{nec title|SX-Aurora|arch}} | ||
| − | {{microarchitecture}} | + | {{microarchitecture |
| + | |atype=VPU | ||
| + | |name=SX-Aurora | ||
| + | |designer=NEC | ||
| + | |manufacturer=TSMC | ||
| + | |introduction=2018 | ||
| + | |cores=8 | ||
| + | |type=Superscalar | ||
| + | |type 2=Pipelined | ||
| + | |oooe=Yes | ||
| + | |speculative=Yes | ||
| + | |renaming=Yes | ||
| + | |stages=8 | ||
| + | |decode=4-way | ||
| + | |l1i=32 KiB | ||
| + | |l1i per=core | ||
| + | |l1d=32 KiB | ||
| + | |l1d per=core | ||
| + | |l2=256 KiB | ||
| + | |l2 per=core | ||
| + | |l3=16 MiB | ||
| + | |l3 per=chip | ||
| + | |predecessor=SX-ACE | ||
| + | |predecessor link=nec/microarchitectures/sx-ace | ||
| + | }} | ||
'''SX-Aurora''' is [[NEC]]'s successor to the {{\\|SX-ACE}}, a [[16 nm]] microarchitecture for [[vector processors]] first introduced in [[2018]]. | '''SX-Aurora''' is [[NEC]]'s successor to the {{\\|SX-ACE}}, a [[16 nm]] microarchitecture for [[vector processors]] first introduced in [[2018]]. | ||
Revision as of 12:46, 21 November 2018
| Edit Values | |
| SX-Aurora µarch | |
| General Info | |
| Arch Type | VPU |
| Designer | NEC |
| Manufacturer | TSMC |
| Introduction | 2018 |
| Core Configs | 8 |
| Pipeline | |
| Type | Superscalar, Pipelined |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 8 |
| Decode | 4-way |
| Cache | |
| L1I Cache | 32 KiB/core |
| L1D Cache | 32 KiB/core |
| L2 Cache | 256 KiB/core |
| L3 Cache | 16 MiB/chip |
| Succession | |
SX-Aurora is NEC's successor to the SX-ACE, a 16 nm microarchitecture for vector processors first introduced in 2018.
Facts about "SX-Aurora - Microarchitectures - NEC"
| codename | SX-Aurora + |
| core count | 8 + |
| designer | NEC + |
| first launched | 2018 + |
| full page name | nec/microarchitectures/sx-aurora + |
| instance of | microarchitecture + |
| manufacturer | TSMC + |
| name | SX-Aurora + |
| pipeline stages | 8 + |