From WikiChip
Difference between revisions of "apm/microarchitectures/storm"
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*** 8 MiB | *** 8 MiB | ||
*** 64 B/line | *** 64 B/line | ||
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+ | == Bibliography == | ||
+ | * Paramesh Gopi, Gaurav Singh, Greg Favor. ''"X-Gene: 64-bit ARM CPU and SoC."'' Hot Chips 24 Symposium (HCS), 2012 IEEE. IEEE, 2012. |
Revision as of 19:39, 25 September 2018
Edit Values | |
Storm µarch | |
General Info | |
Arch Type | CPU |
Designer | AppliedMicro |
Manufacturer | TSMC |
Introduction | 2011 |
Process | 40 nm |
Core Configs | 8 |
Pipeline | |
Type | Superscalar |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Instructions | |
ISA | ARMv8 |
Succession | |
Storm is AppliedMicro first custom ARM microarchitecture for servers. Storm-based microprocessors were sold under the X-Gene 1 brand of server microprocessors.
Codenames
Codename | Description |
---|---|
Potenza | codename for the core and memory sub-system |
Technology
Storm is fabricated on TSMC's 40 nm bluk CMOS.
Architecture
Memory Hierarchy
- Cache
- L1I
- 32 KiB, 8-way set associative
- Per core
- ECC and Parity protection
- 32 KiB, 8-way set associative
- L1D
- 32 KiB, 8-way set associative
- Per core
- 64 B/line
- Write-through with write-combining
- ECC and Parity protection
- 32 KiB, 8-way set associative
- L2
- 256 KB
- Per process module (2 cores)
- Inclusive of L1 write-thru data caches
- 64 B/line
- ECC and Parity protection
- 256 KB
- L3
- 8 MiB
- 64 B/line
- L1I
Bibliography
- Paramesh Gopi, Gaurav Singh, Greg Favor. "X-Gene: 64-bit ARM CPU and SoC." Hot Chips 24 Symposium (HCS), 2012 IEEE. IEEE, 2012.
Facts about "Storm - Microarchitectures - AppliedMicro"
codename | Storm + |
core count | 8 + |
designer | AppliedMicro + |
first launched | 2011 + |
full page name | apm/microarchitectures/storm + |
instance of | microarchitecture + |
instruction set architecture | ARMv8 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Storm + |
process | 40 nm (0.04 μm, 4.0e-5 mm) + |