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{{apm title|Skylark|arch}}
 
{{apm title|Skylark|arch}}
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{{microarchitecture}}
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{{microarchitecture
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|atype=CPU
 +
|name=Skylark
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|designer=AppliedMicro
 +
|designer 2=Ampere Computing
 +
|manufacturer=TSMC
 +
|introduction=2018
 +
|process=16 nm
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|cores=32
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|type=Superscalar
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|oooe=Yes
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|speculative=Yes
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|renaming=Yes
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|isa=ARMv8
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|predecessor=Shadowcat
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|predecessor link=apm/microarchitectures/shadowcat
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|successor=Quicksilver
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|successor link=ampere computing/microarchitectures/quicksilver
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}}
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'''Skylark''' is [[AppliedMicro]]'s successor to {{\\|Shadowcat}}, a [[16 nm]] [[ARM]] microarchitecture for servers. This microarcitecture was eventually acquired by [[Ampere Computing]] which has brought it to market under the {{ampere|eMAG}} brand.
 +
 
 +
== Release Date ==
 +
[[File:apm roadmap x-gene 1-3.png|right|400px]]
 +
Skylark was first announced at [[Hot Chips]] 26 in [[2014]] with the goal of samples starting around the end of [[2015]]. In November of 2016, [[AppliedMicro]] was acquired by [[MACOM]]. Samples for Skylark-based processors were finally announced in March 2017. Later the year the architecture designs, team, and other assets were acquired by [[Ampere Computing]] which has finally brought the product to market in early 2018 with mass production planned for mid-2018.
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 +
== Technology ==
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Skylark is manufactured on [[TSMC]]'s [[16 nm process|16FF+ process]].
 +
 
 +
== Architecture ==
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=== Key changes from {{\\|Shadowcat}} ===
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* [[16 nm process|16 nm (16FF+) process]] (from [[28 nm]])
 +
* Faster frequency (3.3 GHz, up from 2.8 GHz)
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* 4x core count (32 cores, up from 8)
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** 4x processor modules (16 duplexes, up from 4)
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** Coherent network improved for large core count
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* 4x L3 (32 MiB, up from 8 MiB)
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* I/O
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** {{arm|Generic Interrupt Controller}} (GIC) v3.0 (up from v2.0)
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** 5.25x more PCIe lanes(42 lanes, up from 8)
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*** 8 controllers (up from 1)
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* Memory
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** 2x memory channels (8 channels, up from 4)
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*** 2x DIMMs (16 DIMMs, up from 8)
 +
*** DDR4 (from DDR4)
 +
*** Faster DDR rates (2666 MT/s, up from 1866 MT/s)
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** 2.86x Higher bandwidth (170.7 GB/s, up from 59.73 GB/s)
 +
* Package
 +
** 3211-pin (up from 1624)
 +
 
 +
{{expand list}}
 +
 
 +
== Block Diagram ==
 +
=== Entire SoC ===
 +
:[[File:skylark block diagram.svg|800px]]
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 +
=== Memory Hierarchy ===
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* Cache
 +
** L1I Cache
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*** 32 KiB
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** L1D Cache
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*** 32 KiB
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** L2
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*** 256 KiB
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*** Shared per processor module
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** L3
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*** 32 MiB
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*** ECC protected
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*** Shared by entire chip
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* System [[DRAM]]
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** 8 channels
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** 8 B/cycle/channel (@ memory clock)
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** Up to DDR4 @ 2666 MT/s
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** Up to 1 TiB
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** ECC support,
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== Overview ==
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{{empty section}}
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== Bibliography ==
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* AppliedMicro. (June, 2016). personal communication.
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* Ampere Computing. (February 5, 2018). personal communication.
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* Ampere Computing. (September 19, 2018). personal communication.
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* David Schor. (September 19, 2018). "''[https://fuse.wikichip.org/news/1663/ampere-ships-first-gen-arm-server-processors/ Ampere Ships First Gen ARM Server Processors]''".

Latest revision as of 19:13, 25 September 2018

Edit Values
Skylark µarch
General Info
Arch TypeCPU
DesignerAppliedMicro, Ampere Computing
ManufacturerTSMC
Introduction2018
Process16 nm
Core Configs32
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAARMv8
Succession

Skylark is AppliedMicro's successor to Shadowcat, a 16 nm ARM microarchitecture for servers. This microarcitecture was eventually acquired by Ampere Computing which has brought it to market under the eMAG brand.

Release Date[edit]

apm roadmap x-gene 1-3.png

Skylark was first announced at Hot Chips 26 in 2014 with the goal of samples starting around the end of 2015. In November of 2016, AppliedMicro was acquired by MACOM. Samples for Skylark-based processors were finally announced in March 2017. Later the year the architecture designs, team, and other assets were acquired by Ampere Computing which has finally brought the product to market in early 2018 with mass production planned for mid-2018.

Technology[edit]

Skylark is manufactured on TSMC's 16FF+ process.

Architecture[edit]

Key changes from Shadowcat[edit]

  • 16 nm (16FF+) process (from 28 nm)
  • Faster frequency (3.3 GHz, up from 2.8 GHz)
  • 4x core count (32 cores, up from 8)
    • 4x processor modules (16 duplexes, up from 4)
    • Coherent network improved for large core count
  • 4x L3 (32 MiB, up from 8 MiB)
  • I/O
  • Memory
    • 2x memory channels (8 channels, up from 4)
      • 2x DIMMs (16 DIMMs, up from 8)
      • DDR4 (from DDR4)
      • Faster DDR rates (2666 MT/s, up from 1866 MT/s)
    • 2.86x Higher bandwidth (170.7 GB/s, up from 59.73 GB/s)
  • Package
    • 3211-pin (up from 1624)

This list is incomplete; you can help by expanding it.

Block Diagram[edit]

Entire SoC[edit]

skylark block diagram.svg

Memory Hierarchy[edit]

  • Cache
    • L1I Cache
      • 32 KiB
    • L1D Cache
      • 32 KiB
    • L2
      • 256 KiB
      • Shared per processor module
    • L3
      • 32 MiB
      • ECC protected
      • Shared by entire chip
  • System DRAM
    • 8 channels
    • 8 B/cycle/channel (@ memory clock)
    • Up to DDR4 @ 2666 MT/s
    • Up to 1 TiB
    • ECC support,

Overview[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Bibliography[edit]

  • AppliedMicro. (June, 2016). personal communication.
  • Ampere Computing. (February 5, 2018). personal communication.
  • Ampere Computing. (September 19, 2018). personal communication.
  • David Schor. (September 19, 2018). "Ampere Ships First Gen ARM Server Processors".
Retrieved from "https://en.wikichip.org/w/index.php?title=apm/microarchitectures/skylark&oldid=82755"
Facts about "Skylark - Microarchitectures - AppliedMicro"
RDF feed
codenameSkylark +
core count32 +
designerAppliedMicro + and Ampere Computing +
first launched2018 +
full page nameapm/microarchitectures/skylark +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerTSMC +
microarchitecture typeCPU +
nameSkylark +
process16 nm (0.016 μm, 1.6e-5 mm) +