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Difference between revisions of "apm/microarchitectures/skylark"
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== Architecture == | == Architecture == | ||
=== Key changes from {{\\|Shadowcat}} === | === Key changes from {{\\|Shadowcat}} === | ||
| − | {{ | + | * [[16 nm process|16 nm (16FF+) process]] (from [[28 nm]]) |
| + | |||
| + | {{expand list}} | ||
| + | == Block Diagram == | ||
| + | === Entire SoC === | ||
| + | :[[File:skylark block diagram.svg|800px]] | ||
=== Memory Hierarchy === | === Memory Hierarchy === | ||
| − | + | * Cache | |
| + | ** L1I Cache | ||
| + | *** 32 KiB | ||
| + | ** L1D Cache | ||
| + | *** 32 KiB | ||
| + | ** L2 | ||
| + | *** 256 KiB | ||
| + | *** Shared per processor module | ||
| + | ** L3 | ||
| + | *** 32 MiB | ||
| + | * System [[DRAM]] | ||
| + | ** 8 channels | ||
| + | ** 8 B/cycle/channel (@ memory clock) | ||
| + | ** Up to DDR4 @ 2666 MT/s | ||
| + | ** Up to 1 TiB | ||
== Core == | == Core == | ||
{{empty section}} | {{empty section}} | ||
Revision as of 13:09, 21 September 2018
| Edit Values | |
| Skylark µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | AppliedMicro, Ampere Computing |
| Manufacturer | TSMC |
| Introduction | 2018 |
| Process | 16 nm |
| Core Configs | 32 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | ARMv8 |
| Succession | |
Skylark is AppliedMicro's successor to Shadowcat, a 16 nm ARM microarchitecture for servers. This microarcitecture was eventually acquired by Ampere Computing which has brought it to market.
Contents
Release Date
Skylark was first announced at Hot Chips 26 in 2014 with the goal of samples starting around the end of 2015. In November of 2016, AppliedMicro was acquired by MACOM. Samples for Skylark-based processors were finally announced in March 2017. Later the year the architecture designs, team, and other assets were acquired by Ampere Computing which has finally brought the product to market in early 2018 with mass production planned for mid-2018.
Technology
Skylark is manufactured on TSMC's 16FF+ process.
Architecture
Key changes from Shadowcat
- 16 nm (16FF+) process (from 28 nm)
This list is incomplete; you can help by expanding it.
Block Diagram
Entire SoC
Memory Hierarchy
- Cache
- L1I Cache
- 32 KiB
- L1D Cache
- 32 KiB
- L2
- 256 KiB
- Shared per processor module
- L3
- 32 MiB
- L1I Cache
- System DRAM
- 8 channels
- 8 B/cycle/channel (@ memory clock)
- Up to DDR4 @ 2666 MT/s
- Up to 1 TiB
Core
 |
This section is empty; you can help add the missing info by editing this page. |
Facts about "Skylark - Microarchitectures - AppliedMicro"
| codename | Skylark + |
| core count | 32 + |
| designer | AppliedMicro + and Ampere Computing + |
| first launched | 2018 + |
| full page name | apm/microarchitectures/skylark + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Skylark + |
| process | 16 nm (0.016 μm, 1.6e-5 mm) + |