Difference between revisions of "mediatek/helio/mt6795t"

	Edit Values
	MediaTek Helio X10 T
	General Info
Designer	MediaTek,; ARM Holdings
Manufacturer	TSMC
Model Number	Helio X10 T
Part Number	MT6795T,; MTK6795T
Market	Mobile, Embedded
Introduction	July 15, 2014 (announced); March 27, 2015 (launched)
	General Specs
Family	Helio
Series	Helio X
Frequency	2,200 MHz
Bus type	AMBA 4 AXI
	Microarchitecture
ISA	ARMv8 (ARM)
Microarchitecture	Cortex-A53
Core Name	Cortex-A53
Process	28 nm
Technology	CMOS
Word Size	64 bit
Cores	8
Threads	8
Max Memory	4 GiB
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
	Electrical
Vcore	1 V
VI/O	1.8 V, 2.8 V, 3.3 V
OP Temperature	-20 °C – 80 °C
Tjunction	– 125 °C
Tstorage	0 °C – 125 °C

Latest revision as of 08:36, 22 August 2018

Helio X10 T (MT6795T; T for turbo) is a 64-bit octa-core ARM LTE system on a chip designed by MediaTek and introduced in early-2015. This SoC, which incorporates eight Cortex-A53 cores and is manufactured on TSMC's 28 nm process, operates at up to 2.2 GHz and supports dual-channel LPDDR3-1866. This chip incorporates the PowerVR G6200 IGP operating at 700 MHz. This SoC has a modem supporting LTE User Equipment (UE) category 4. This "turbo" variant of the X10 operates at 10% higher frequency.

This SoC is made of 2 clusters of 4-core each (Cortex-A53) linked together via a CCI-400, a NEON engine, and Cortex-R4 core for the second MCU subsystem.

Cache[edit]

Main article: Cortex-A53 § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

512 KiB

524,288 B
0.5 MiB

L1I$	256 KiB 262,144 B 0.25 MiB	8x32 KiB	2-way set associative
L1D$	256 KiB 262,144 B 0.25 MiB	8x32 KiB	4-way set associative

L2$

2 MiB

2,048 KiB
2,097,152 B
0.00195 GiB

		2x1 MiB	16-way set associative

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	LPDDR3-1866
Supports ECC	No
Max Mem	4 GiB
Controllers	1
Channels	2
Width	32 bit
Max Bandwidth	13.91 GiB/s 14,243.84 MiB/s 14.936 GB/s 14,935.749 MB/s 0.0136 TiB/s 0.0149 TB/s
Bandwidth	Single 6.95 GiB/s Double 13.91 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

Expansion Options

USB

Revision	2.0, 3.0
Ports	8

UART

GP I/O	Yes

Graphics[edit]

[Edit/Modify IGP Info]

Integrated Graphics Information

GPU

PowerVR G6200

Designer

Imagination Technologies

Max Displays

2

Frequency

700 MHz

0.7 GHz
700,000 KHz

Output

DSI

Max Resolution

DSI	2560x1600

Standards

Direct3D	10.0
OpenGL	3.2
OpenCL	1.2
OpenGL ES	3.1
Vulkan	1.0

OpenGL ES 3.0 3D graphic accelerator capable of processing 175M tri/sec and 2,800M pixel/sec @ 700 MHz
OpenVG 1.1 vector graphics accelerator

Wireless[edit]

Wireless Communications

Cellular

2G

CSD		Yes
GSM		Yes
GPRS		Yes
EDGE		Yes

3G

UMTS

TD-SCDMA	Yes
DC-HSDPA	Yes
HSUPA	Yes

4G

LTE Advanced

E-UTRAN	Yes
UE Cat	4

Image[edit]

Integrated image signal processor supports 20 MP
Supports image stabilization
Supports video stabilization
Supports noise reduction
Supports lens shading correction
Supports AE/AWB/AF
Supports edge enhancement
Supports face detection and visual tracking
Hardware JPEG encoder

Video[edit]

HEVC decoder 4k2k @ 30fps
H.264 decoder (30fps/40Mbps)
Sorenson H.263/H.263 decoder (1080p @ 60fps/40Mbps)
MPEG-4 SP/ASP decoder (1080p @ 60fps/40Mbps)
DIVX4/DIVX5/DIVX6/DIVX HD/XVID decoder (1080p @ 60fps/40Mbps)
VP8 / VC-1 decoders
MPEG-4 / H.263 / H.264 / HEVC encoders

Audio[edit]

Audio content sampling rates 8kHz to 192kHz
Audio content sampling format 8-bit/16-bit/24-bit Mono/Stereo
I2S, PCM
Encode: AMR-NB, AMR-WB, AAC, OGG, ADPCM
Decode: WAV, MP3, MP2, AAC, AMR-NB, AMR-WB, MIDI, Vorbis, APE, AAC-plus v1, AAC-plus v2, FLAC, WMA, ADPCM
7.1 channel MHL output

Utilizing devices[edit]

Meizu MX5
LeEco Le 1s
Xiaomi Redmi Note 2
HTC One X9
HTC One M9+
HTC One ME

This list is incomplete; you can help by expanding it.

@@ Line 1: / Line 1: @@
-{{mediatek title|Helio X10 (MT6795T)}}
+{{mediatek title|Helio X10 T (MT6795T)}}
-{{mpu
+{{chip
-| name                = MediaTek Helio X10
+| name                = MediaTek Helio X10 T
 | no image            = yes
 | image               =
@@ Line 9: / Line 9: @@
 | designer 2          = ARM Holdings
 | manufacturer        = TSMC
-| model number        = Helio X10
+| model number        = Helio X10 T
 | part number         = MT6795T
+| part number 2       = MTK6795T
 | market              = Mobile
 | market 2            = Embedded
@@ Line 50: / Line 51: @@
 | max memory          = 4 GiB
-| electrical          = Yes
 | power               =
 | v core              = 1 V
@@ Line 84: / Line 85: @@
 | package 0 height    = 0.78 mm
 }}
-'''Helio X10''' ('''MT6795T''' t for ''turbo'') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and introduced in early-[[2014]]. This SoC, which incorporates eight {{armh|Cortex-A53}} cores and is manufactured on TSMC's [[28 nm process]], operates at up to 2.2 GHz and supports dual-channel LPDDR3-933. This chip incorporates the {{imgtec|PowerVR G6200}} [[IGP]] operating at 700 MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) category 4. This "turbo" variant of the X10 operates at 10% higher frequency.
+'''Helio X10 T''' ('''MT6795T'''; T for ''turbo'') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and introduced in early-[[2015]]. This SoC, which incorporates eight {{armh|Cortex-A53}} cores and is manufactured on TSMC's [[28 nm process]], operates at up to 2.2 GHz and supports dual-channel LPDDR3-1866. This chip incorporates the {{imgtec|PowerVR G6200}} [[IGP]] operating at 700 MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) category 4. This "turbo" variant of the X10 operates at 10% higher frequency.
 This SoC is made of 2 clusters of 4-core each ({{armh|Cortex-A53}}) linked together via a {{armh|CCI-400}}, a {{armh|NEON}} engine, and {{armh|Cortex-R4}} core for the second MCU subsystem.
@@ Line 105: / Line 106: @@
 == Memory controller ==
 {{memory controller
-|type=DDR3-933
+|type=LPDDR3-1866
 |ecc=No
 |max mem=4 GiB
 |controllers=1
 |channels=2
-|max bandwidth=13.9 GiB/s
+|width=32 bit
+|max bandwidth=13.91 GiB/s
 |bandwidth schan=6.95 GiB/s
-|bandwidth dchan=13.9 GiB/s
+|bandwidth dchan=13.91 GiB/s
 }}
@@ Line 141: / Line 143: @@
 | opencl ver          = 1.2
 | opengl ver          = 3.2
-| opencl es ver       = 3.1
+| opengl es ver       = 3.1
 | vulkan ver          = 1.0
 }}
@@ Line 209: / Line 211: @@
 * [[used by::HTC One X9]]
 * [[used by::HTC One M9+]]
+* [[used by::HTC One ME]]
 {{expand list}}

base frequency	2,200 MHz (2.2 GHz, 2,200,000 kHz) +
bus type	AMBA 4 AXI +
core count	8 +
core name	Cortex-A53 +
core voltage	1 V (10 dV, 100 cV, 1,000 mV) +
designer	MediaTek + and ARM Holdings +
family	Helio +
first announced	July 15, 2014 +
first launched	March 27, 2015 +
full page name	mediatek/helio/mt6795t +
has 2g support	true +
has 3g support	true +
has 4g support	true +
has csd support	true +
has dc-hsdpa support	true +
has e-utran support	true +
has ecc memory support	false +
has edge support	true +
has gprs support	true +
has gsm support	true +
has hsupa support	true +
has lte advanced support	true +
has td-scdma support	true +
has umts support	true +
instance of	microprocessor +
integrated gpu	PowerVR G6200 +
integrated gpu base frequency	700 MHz (0.7 GHz, 700,000 KHz) +
integrated gpu designer	Imagination Technologies +
io voltage	1.8 V (18 dV, 180 cV, 1,800 mV) +, 2.8 V (28 dV, 280 cV, 2,800 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) +
isa	ARMv8 +
isa family	ARM +
l1$ size	512 KiB (524,288 B, 0.5 MiB) +
l1d$ description	4-way set associative +
l1d$ size	256 KiB (262,144 B, 0.25 MiB) +
l1i$ description	2-way set associative +
l1i$ size	256 KiB (262,144 B, 0.25 MiB) +
l2$ description	16-way set associative +
l2$ size	2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldate	March 27, 2015 +
manufacturer	TSMC +
market segment	Mobile + and Embedded +
max cpu count	1 +
max junction temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
max memory	4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max memory bandwidth	13.91 GiB/s (14,243.84 MiB/s, 14.936 GB/s, 14,935.749 MB/s, 0.0136 TiB/s, 0.0149 TB/s) +
max memory channels	2 +
max operating temperature	80 °C +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Cortex-A53 +
min operating temperature	-20 °C +
min storage temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
model number	Helio X10 T +
name	MediaTek Helio X10 T +
part number	MT6795T + and MTK6795T +
process	28 nm (0.028 μm, 2.8e-5 mm) +
series	Helio X +
smp max ways	1 +
supported memory type	LPDDR3-1866 +
technology	CMOS +
thread count	8 +
used by	Meizu MX5 +, LeEco Le 1s +, Xiaomi Redmi Note 2 +, HTC One X9 +, HTC One M9+ + and HTC One ME +
user equipment category	4 +
word size	64 bit (8 octets, 16 nibbles) +

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