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| [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || style="text-align: left;" | Enthusiasts/High Performance ({{intel|Skylake X|X|l=core}}) || ?-? || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
 
| [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || style="text-align: left;" | Enthusiasts/High Performance ({{intel|Skylake X|X|l=core}}) || ?-? || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
 
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| [[File:core i9x logo.png|50px|link=intel/core_i9]] || {{intel|Core i9}} || style="text-align: left;" | Enthusiasts/High Performance || [[10 cores|10]] - [[28 cores|28]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
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| [[File:core i9x logo.png|50px|link=intel/core_i9]] || {{intel|Core i9}} || style="text-align: left;" | Enthusiasts/High Performance || ?-? || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
 
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! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="7" | Differentiating Features
 
! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="7" | Differentiating Features
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! Cores !! {{intel|Hyper-Threading|HT}} !! {{intel|Turbo Boost|TBT}} !! {{x86|AVX-512}} !! AVX-512 Units !! {{intel|Ultra Path Interconnect|UPI}} links !! Scalability
 
! Cores !! {{intel|Hyper-Threading|HT}} !! {{intel|Turbo Boost|TBT}} !! {{x86|AVX-512}} !! AVX-512 Units !! {{intel|Ultra Path Interconnect|UPI}} links !! Scalability
 
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| [[File:xeon logo (2015).png|50px|link=intel/xeon d]] || {{intel|Xeon D}} || style="text-align: left;" | Dense servers / edge computing || [[4 cores|4]]-[[18 cores|18]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 1 || colspan="2" {{tchk|no}}
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| [[File:xeon logo (2015).png|50px|link=intel/xeon d]] || {{intel|Xeon D}} || style="text-align: left;" | Dense servers / edge computing || ?-? || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 1 || colspan="2" {{tchk|no}}
 
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| [[File:xeon logo (2015).png|50px|link=intel/xeon w]] || {{intel|Xeon W}} || style="text-align: left;" | Business workstations || [[4 cores|4]]-[[18 cores|18]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 2 || colspan="2" {{tchk|no}}
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| [[File:xeon logo (2015).png|50px|link=intel/xeon w]] || {{intel|Xeon W}} || style="text-align: left;" | Business workstations || ?-? || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 2 || colspan="2" {{tchk|no}}
 
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| [[File:xeon bronze (2017).png|50px]] || {{intel|Xeon Bronze}} || style="text-align: left;" | Entry-level performance / <br>Cost-sensitive || [[6 cores|6]] - [[8 cores|8]] || {{tchk|no}} || {{tchk|no}} || {{tchk|yes}} || 1 || 2 || Up to 2
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| [[File:xeon bronze (2017).png|50px]] || {{intel|Xeon Bronze}} || style="text-align: left;" | Entry-level performance / <br>Cost-sensitive || ?-? || {{tchk|no}} || {{tchk|no}} || {{tchk|yes}} || 1 || 2 || Up to 2
 
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| [[File:xeon silver (2017).png|50px]] || {{intel|Xeon Silver}} || style="text-align: left;" | Mid-range performance / <br>Efficient lower power || [[4 cores|4]] - [[12 cores|12]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 1 || 2 || Up to 2
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| [[File:xeon silver (2017).png|50px]] || {{intel|Xeon Silver}} || style="text-align: left;" | Mid-range performance / <br>Efficient lower power || ?-? || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 1 || 2 || Up to 2
 
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| rowspan="2" | [[File:xeon gold (2017).png|50px]] || {{intel|Xeon Gold}} 5000 || style="text-align: left;" | High performance || [[4 cores|4]] - [[14 cores|14]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 1 || 2 || Up to 4
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| rowspan="2" | [[File:xeon gold (2017).png|50px]] || {{intel|Xeon Gold}} 5000 || style="text-align: left;" | High performance || ?-? || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 1 || 2 || Up to 4
 
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| {{intel|Xeon Gold}} 6000 || style="text-align: left;" | Higher performance || [[6 cores|6]] - [[22 cores|22]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 2  || 3 || Up to 4
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| {{intel|Xeon Gold}} 6000 || style="text-align: left;" | Higher performance || ?-? || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 2  || 3 || Up to 4
 
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| [[File:xeon platinum (2017).png|50px]] || {{intel|Xeon Platinum}} || style="text-align: left;" | Highest performance / flexibility || [[4 cores|4]] - [[28 cores|28]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 2 || 3 || Up to 8
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| [[File:xeon platinum (2017).png|50px]] || {{intel|Xeon Platinum}} || style="text-align: left;" | Highest performance / flexibility || ?-? || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 2 || 3 || Up to 8
 
|}
 
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Revision as of 10:06, 29 June 2018

Edit Values
Cascade Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2018
Process14 nm
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache1 MiB/core
16-way set associative
L3 Cache1.375 MiB/core
11-way set associative
Cores
Core NamesCascade Lake X,
Cascade Lake SP
Succession
Contemporary
Coffee Lake

Cascade Lake (CLX/CSL) is Intel's successor to Skylake, a 14 nm microarchitecture for enthusiasts and servers. Cascade Lake is the "Optimization" phase as part of Intel's PAO model.

For desktop enthusiasts, Cascade Lake is branded Core i7, and Core i9 processors (under the Core X series). For scalable server class processors, Intel branded it as Xeon Bronze, Xeon Silver, Xeon Gold, and Xeon Platinum.

Codenames

Core Abbrev Target
Cascade Lake X CSL-X High-end desktops & enthusiasts market
Cascade Lake W CSL-W Enterprise/Business workstations
Cascade Lake SP CSL-SP Server Scalable Processors
Cascade Lake AP CSL-AP Server Advanced Processors

Brands

Cascade Lake is sold under eight different families.

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
Logo Family General Description Differentiating Features
Cores HT AVX AVX2 AVX-512 TBT ECC
core i7 logo (2015).png Core i7 Enthusiasts/High Performance (X)  ?-? ✔ ✔ ✔ ✔ ✔ ✘
core i9x logo.png Core i9 Enthusiasts/High Performance  ?-? ✔ ✔ ✔ ✔ ✔ ✘
Logo Family General Description Differentiating Features
Cores HT TBT AVX-512 AVX-512 Units UPI links Scalability
xeon logo (2015).png Xeon D Dense servers / edge computing  ?-? ✔ ✔ ✔ 1 ✘
xeon logo (2015).png Xeon W Business workstations  ?-? ✔ ✔ ✔ 2 ✘
xeon bronze (2017).png Xeon Bronze Entry-level performance /
Cost-sensitive 		 ?-? ✘ ✘ ✔ 1 2 Up to 2
xeon silver (2017).png Xeon Silver Mid-range performance /
Efficient lower power 		 ?-? ✔ ✔ ✔ 1 2 Up to 2
xeon gold (2017).png Xeon Gold 5000 High performance  ?-? ✔ ✔ ✔ 1 2 Up to 4
Xeon Gold 6000 Higher performance  ?-? ✔ ✔ ✔ 2 3 Up to 4
xeon platinum (2017).png Xeon Platinum Highest performance / flexibility  ?-? ✔ ✔ ✔ 2 3 Up to 8

Release Dates

Cascade Lake is expected to be released in mid-2018.

Process Technology

Cascade Lake is fabricated on Intel's 3rd generation enhanced 14nm++ process.

Architecture

As with Skylake, Cascade Lake is also based on the Purley platform and is designed as a drop-in upgrade.

Key changes from Skylake

  • Architectural improvements (specifics unknown yet)
  • Core
  • Package
    • Selected SKUs with Arria 10 FPGAs in a MCP
  • Memory
    • 2933 MT/s DDR4 (up from 2666 MT/s)
    • Support for DDR-T / Optane DIMMs

This list is incomplete; you can help by expanding it.

New instructions

Cascade Lake introduced a number of new instructions:

Block Diagram

New text document.svg This section is empty; you can help add the missing info by editing this page.
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Facts about "Cascade Lake - Microarchitectures - Intel"
RDF feed
codenameCascade Lake +
designerIntel +
first launched2018 +
full page nameintel/microarchitectures/cascade lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameCascade Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process14 nm (0.014 μm, 1.4e-5 mm) +