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Difference between revisions of "graphcore/ipu"
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{{graphcore title|IPU}}
 
{{graphcore title|IPU}}
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{{ic family
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| title            = IPU
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| image            =
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| caption          =
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| no image          = Yes
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| developer        = Graphcore
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| manufacturer      = TSMC
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| type              = Neural Processor
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| first announced  =
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| first launched    =
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| isa              =
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| microarch        = Colossus
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| word              =
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| proc              = 16 nm
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| tech              = CMOS
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| clock            =
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| clock min        =
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| clock max        =
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| package          =
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| socket            =
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| succession      =
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| predecessor      =
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| predecessor link =
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| successor        =
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| successor link  =
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}}
 
'''Intelligence Processing Unit''' ('''IPU''') is a family of [[neural processors]] being designed by [[Graphcore]] set to be introduced later this year.
 
'''Intelligence Processing Unit''' ('''IPU''') is a family of [[neural processors]] being designed by [[Graphcore]] set to be introduced later this year.
  
  
 
{{stub}}
 
{{stub}}

Latest revision as of 09:49, 25 June 2018

IPU
Developer Graphcore
Manufacturer TSMC
Type Neural Processor
µarch Colossus
Process 16 nm
0.016 μm
1.6e-5 mm
Technology CMOS

Intelligence Processing Unit (IPU) is a family of neural processors being designed by Graphcore set to be introduced later this year.


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Facts about "IPU - Graphcore"
designerGraphcore +
full page namegraphcore/ipu +
instance ofintegrated circuit family +
main designerGraphcore +
manufacturerTSMC +
microarchitectureColossus +
nameIPU +
process16 nm (0.016 μm, 1.6e-5 mm) +
technologyCMOS +