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Difference between revisions of "graphcore/ipu"
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{{graphcore title|IPU}} | {{graphcore title|IPU}} | ||
+ | {{ic family | ||
+ | | title = IPU | ||
+ | | image = | ||
+ | | caption = | ||
+ | | no image = Yes | ||
+ | | developer = Graphcore | ||
+ | | manufacturer = TSMC | ||
+ | | type = Neural Processor | ||
+ | | first announced = | ||
+ | | first launched = | ||
+ | | isa = | ||
+ | | microarch = Colossus | ||
+ | | word = | ||
+ | | proc = 16 nm | ||
+ | | tech = CMOS | ||
+ | | clock = | ||
+ | | clock min = | ||
+ | | clock max = | ||
+ | | package = | ||
+ | | socket = | ||
+ | |||
+ | | succession = | ||
+ | | predecessor = | ||
+ | | predecessor link = | ||
+ | | successor = | ||
+ | | successor link = | ||
+ | }} | ||
'''Intelligence Processing Unit''' ('''IPU''') is a family of [[neural processors]] being designed by [[Graphcore]] set to be introduced later this year. | '''Intelligence Processing Unit''' ('''IPU''') is a family of [[neural processors]] being designed by [[Graphcore]] set to be introduced later this year. | ||
{{stub}} | {{stub}} |
Latest revision as of 09:49, 25 June 2018
IPU | |
Developer | Graphcore |
Manufacturer | TSMC |
Type | Neural Processor |
µarch | Colossus |
Process | 16 nm 0.016 μm
1.6e-5 mm |
Technology | CMOS |
Intelligence Processing Unit (IPU) is a family of neural processors being designed by Graphcore set to be introduced later this year.
This article is still a stub and needs your attention. You can help improve this article by editing this page and adding the missing information. |
Facts about "IPU - Graphcore"
designer | Graphcore + |
full page name | graphcore/ipu + |
instance of | integrated circuit family + |
main designer | Graphcore + |
manufacturer | TSMC + |
microarchitecture | Colossus + |
name | IPU + |
process | 16 nm (0.016 μm, 1.6e-5 mm) + |
technology | CMOS + |