From WikiChip
Colossus - Graphcore
< graphcore(Redirected from graphcore/colossus (microarch))

Edit Values
Colossus µarch
General Info
Arch TypeNPU
DesignerGraphcore
ManufacturerTSMC
Introduction2018
Process16 nm

Colossus is a 16 nm microarchitecture for high-performance neural processors designed by Graphcore set to be introduced in late-2018.

Etymology[edit]

Codename Colossus was chosen in honor of Tommy Flowers and the Colossus computer.

Process Technology[edit]

Colossus is designed to be fabricated on TSMC's 16 nm FinFET process.

Architecture[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Die[edit]

Floorplan[edit]

  • 16 nm process
  • ~800 mm² die size
  • 23,647,173,309 transistors
  • 1,216 PUs
    • 2 Grids of 608 PUs each
      • 8 x 19 blocks
        • 4 PUs / block
    • 300 MiB on-die memory


colossus floorplan.png


colossus floorplan (annotated).png
Retrieved from "https://en.wikichip.org/w/index.php?title=graphcore/microarchitectures/colossus&oldid=79503"
Facts about "Colossus - Graphcore"
RDF feed
codenameColossus +
designerGraphcore +
first launched2018 +
full page namegraphcore/microarchitectures/colossus +
instance ofmicroarchitecture +
manufacturerTSMC +
nameColossus +
process16 nm (0.016 μm, 1.6e-5 mm) +