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Colossus µarch
General Info
Arch Type	NPU
Designer	Graphcore
Manufacturer	TSMC
Introduction	2018
Process	16 nm

Colossus is a 16 nm microarchitecture for high-performance neural processors designed by Graphcore set to be introduced in late-2018.

Etymology

Codename Colossus was chosen in honor of Tommy Flowers and the Colossus computer.

Process Technology

Colossus is designed to be fabricated on TSMC's 16 nm FinFET process.

Architecture

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Die

Floorplan

• 16 nm process
• ~800 mm² die size
• 23,647,173,309 transistors
• 1,216 PUs
  • 2 Grids of 608 PUs each
    • 8 x 19 blocks
      • 4 PUs / block
  • 300 MiB on-die memory