From WikiChip
Difference between revisions of "zhaoxin/kaixian/kx-u5580m"
< zhaoxin‎ | kaixian

 
(7 intermediate revisions by 2 users not shown)
Line 19: Line 19:
 
|bus links=4
 
|bus links=4
 
|bus rate=8 GT/s
 
|bus rate=8 GT/s
 +
|clock multiplier=18
 
|isa=x86-64
 
|isa=x86-64
 
|isa family=x86
 
|isa family=x86
Line 35: Line 36:
 
}}
 
}}
 
'''KaiXian KX-U5580M''' is a {{arch|64}} [[octa-core]] [[x86]] microprocessor designed by [[Zhaoxin]] and introduced in late [[2017]] specifically for the [[Chinese]] market. This processor is fabricated on a [[28 nm process]] based on the {{zhaoxin|WuDaoKou|l=arch}} microarchitecture. The KX-U5580M operates at 1.8 GHz with a TDP of ? W and supports up to 64 GiB of dual-channel DDR4-2133 memory. The KX-U5580M also incorporates an integrated graphics processor.
 
'''KaiXian KX-U5580M''' is a {{arch|64}} [[octa-core]] [[x86]] microprocessor designed by [[Zhaoxin]] and introduced in late [[2017]] specifically for the [[Chinese]] market. This processor is fabricated on a [[28 nm process]] based on the {{zhaoxin|WuDaoKou|l=arch}} microarchitecture. The KX-U5580M operates at 1.8 GHz with a TDP of ? W and supports up to 64 GiB of dual-channel DDR4-2133 memory. The KX-U5580M also incorporates an integrated graphics processor.
 +
 +
 +
{{unknown features}}
 +
 +
 +
== Cache ==
 +
{{main|zhaoxin/microarchitectures/wudaokou#Memory_Hierarchy|l1=WuDaoKou § Cache}}
 +
{{cache size
 +
|l1 cache=512 KiB
 +
|l1i cache=256 KiB
 +
|l1i break=8x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=256 KiB
 +
|l1d break=8x32 KiB
 +
|l1d desc=8-way set associative
 +
|l2 cache=8 MiB
 +
|l2 break=2x4 MiB
 +
|l2 desc=32-way set associative
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2133
 +
|ecc=No
 +
|max mem=64 GiB
 +
|controllers=1
 +
|channels=2
 +
|max bandwidth=31.79 GiB/s
 +
|bandwidth schan=15.89 GiB/s
 +
|bandwidth dchan=31.79 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
{{expansions main
 +
|
 +
{{expansions entry
 +
|type=PCIe
 +
|pcie revision=3.0
 +
|pcie lanes=24
 +
}}
 +
}}
 +
 +
== Graphics ==
 +
{{integrated graphics
 +
| gpu                = ?
 +
| device id          =
 +
| designer            = Zhaoxin
 +
| execution units    =
 +
| max displays        = 3
 +
| max memory          =
 +
| frequency          = ? MHz
 +
| max frequency      =
 +
 +
| output crt          =
 +
| output sdvo        =
 +
| output dsi          =
 +
| output edp          = Yes
 +
| output dp          = Yes
 +
| output hdmi        = Yes
 +
| output vga          = Yes
 +
| output dvi          =
 +
 +
| directx ver        = 11.1
 +
| opengl ver        =
 +
| opencl ver        =
 +
| hdmi ver          = 1.4b
 +
| dp ver            = 1.2a
 +
| edp ver            = 1.3
 +
| max res hdmi      = 4096x2304
 +
| max res hdmi freq  =
 +
| max res dp        = 4096x2304
 +
| max res dp freq    = 60 Hz
 +
| max res edp        = 4096x2304
 +
| max res edp freq  = 60 Hz
 +
| max res vga        =
 +
| max res vga freq  =
 +
}}
 +
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=Yes
 +
|avx2=Yes
 +
|avx512f=No
 +
|avx512cd=No
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=No
 +
|avx512dq=No
 +
|avx512vl=No
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|abm=No
 +
|tbm=No
 +
|bmi1=No
 +
|bmi2=No
 +
|fma3=No
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=Yes
 +
|xop=No
 +
|adx=No
 +
|clmul=No
 +
|f16c=No
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=No
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=No
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=Yes
 +
|ht=No
 +
|vpro=No
 +
|vtx=Yes
 +
|vtd=No
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|intqat=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
}}

Latest revision as of 23:28, 26 May 2018

Edit Values
KaiXian KX-U5580M
KX-U5580M.png
KX-U5580M front
General Info
DesignerZhaoxin
ManufacturerHLMC
Model NumberKX-U5580M
Part NumberKX-U5580M
MarketDesktop, Mobile, Embedded
IntroductionDecember 28, 2017 (announced)
December 28, 2017 (launched)
General Specs
FamilyKaiXian
SeriesKX-5000
Frequency1,800 MHz
Bus typePCIe 3.0
Bus rate4 × 8 GT/s
Clock multiplier18
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureWuDaoKou
Process28 nm
Transistors2,100,000,000
TechnologyCMOS
Die187 mm²
Word Size64 bit
Cores8
Threads8
Max Memory64 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Tjunction0 °C – 90 °C

KaiXian KX-U5580M is a 64-bit octa-core x86 microprocessor designed by Zhaoxin and introduced in late 2017 specifically for the Chinese market. This processor is fabricated on a 28 nm process based on the WuDaoKou microarchitecture. The KX-U5580M operates at 1.8 GHz with a TDP of ? W and supports up to 64 GiB of dual-channel DDR4-2133 memory. The KX-U5580M also incorporates an integrated graphics processor.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache[edit]

Main article: WuDaoKou § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  2x4 MiB32-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133
Supports ECCNo
Max Mem64 GiB
Controllers1
Channels2
Max Bandwidth31.79 GiB/s
32,552.96 MiB/s
34.134 GB/s
34,134.253 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 24


Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPU?
DesignerZhaoxin
Max Displays3
Frequency? MHz
"? MHz" is not a number.
OutputDP, eDP, HDMI, VGA
Max Resolution
HDMI4096x2304
DP4096x2304 @60 Hz
eDP4096x2304 @60 Hz
Standards
DirectX11.1
DP1.2a
eDP1.3
HDMI1.4b

Features[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=zhaoxin/kaixian/kx-u5580m&oldid=78807"
Facts about "KaiXian KX-U5580M - Zhaoxin"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
KaiXian KX-U5580M - Zhaoxin#pcie +
base frequency1,800 MHz (1.8 GHz, 1,800,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typePCIe 3.0 +
clock multiplier18 +
core count8 +
designerZhaoxin +
die area187 mm² (0.29 in², 1.87 cm², 187,000,000 µm²) +
familyKaiXian +
first announcedDecember 28, 2017 +
first launchedDecember 28, 2017 +
full page namezhaoxin/kaixian/kx-u5580m +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has ecc memory supportfalse +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Trusted Execution Technology +, Intel VT-x + and Extended Page Tables +
has intel trusted execution technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
integrated gpu? +
integrated gpu designerZhaoxin +
isax86-64 +
isa familyx86 +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description32-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
ldateDecember 28, 2017 +
main imageFile:KX-U5580M.png +
main image captionKX-U5580M front +
manufacturerHLMC +
market segmentDesktop +, Mobile + and Embedded +
max cpu count1 +
max junction temperature363.15 K (90 °C, 194 °F, 653.67 °R) +
max memory65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
max memory bandwidth31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels2 +
microarchitectureWuDaoKou +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model numberKX-U5580M +
nameKaiXian KX-U5580M +
part numberKX-U5580M +
process28 nm (0.028 μm, 2.8e-5 mm) +
seriesKX-5000 +
smp max ways1 +
supported memory typeDDR4-2133 +
technologyCMOS +
thread count8 +
transistor count2,100,000,000 +
word size64 bit (8 octets, 16 nibbles) +