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Difference between revisions of "intel/microarchitectures/larrabee"
< intel‎ | microarchitectures

(Larrabee)
 
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{{intel title|Larrabee|arch}}
 
{{intel title|Larrabee|arch}}
−
{{microarchitecture}}
+
{{microarchitecture
 +
|atype=GPU
 +
|name=Larrabee
 +
|designer=Intel
 +
|manufacturer=Intel
 +
|introduction=August 12, 2008
 +
|phase-out=2010
 +
|process=45 nm
 +
|process 2=32 nm
 +
|cores=8
 +
|cores 2=16
 +
|cores 3=24
 +
|cores 4=32
 +
|cores 5=40
 +
|cores 6=48
 +
|isa=x86
 +
|extension=L1OM
 +
|successor=Knights Ferry
 +
|successor link=intel/microarchitectures/knights_ferry
 +
}}
 
'''Larrabee''' ('''LRB''') was an experimental [[graphics processing unit]] [[microarchitecture]] designed by [[Intel]] for [[gpgpu|General-purpose GPU computing]].
 
'''Larrabee''' ('''LRB''') was an experimental [[graphics processing unit]] [[microarchitecture]] designed by [[Intel]] for [[gpgpu|General-purpose GPU computing]].

Revision as of 16:07, 8 April 2018

Edit Values
Larrabee µarch
General Info
Arch TypeGPU
DesignerIntel
ManufacturerIntel
IntroductionAugust 12, 2008
Phase-out2010
Process45 nm, 32 nm
Core Configs8, 16, 24, 32, 40, 48
Instructions
ISAx86
ExtensionsL1OM
Succession

Larrabee (LRB) was an experimental graphics processing unit microarchitecture designed by Intel for General-purpose GPU computing.

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/larrabee&oldid=77112"
Facts about "Larrabee - Microarchitectures - Intel"
RDF feed
codenameLarrabee +
core count8 +, 16 +, 24 +, 32 +, 40 + and 48 +
designerIntel +
first launchedAugust 12, 2008 +
full page nameintel/microarchitectures/larrabee +
instance ofmicroarchitecture +
instruction set architecturex86 +
manufacturerIntel +
microarchitecture typeGPU +
nameLarrabee +
phase-out2010 +
process45 nm (0.045 μm, 4.5e-5 mm) + and 32 nm (0.032 μm, 3.2e-5 mm) +