From WikiChip
Difference between revisions of "intel/core i5/i5-8500b"
Line 83: | Line 83: | ||
}} | }} | ||
}} | }} | ||
+ | |||
+ | == Graphics == |
Revision as of 11:43, 4 April 2018
Edit Values | |
Core i5-8500B | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | i5-8500B |
Market | Mobile |
Introduction | April 2, 2018 (announced) April 2, 2018 (launched) |
Shop | Amazon |
General Specs | |
Family | Core i5 |
Series | i5-8000 |
Locked | Yes |
Frequency | 3,000 MHz |
Turbo Frequency | 4,100 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 30 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Coffee Lake |
Core Name | Coffee Lake S |
Process | 14 nm |
Technology | CMOS |
Die | 126 mm² |
Word Size | 64 bit |
Cores | 6 |
Threads | 6 |
Max Memory | 64 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Core i5-8500B is a 64-bit hexa-core mid-range performance x86 desktop microprocessor introduced by Intel in early 2018. This processor, which is based on the Coffee Lake microarchitecture, is manufactured on Intel's 3rd generation enhanced 14nm++ process. The i5-8500B operates at a 3 GHz with a TDP of 65 W and a Turbo Boost frequency of up to 4.1 GHz. This chip supports up to 64 GiB of dual-channel DDR4-2666 memory and incorporates Intel's UHD Graphics 630 IGP operating at 350 MHz with a burst frequency of 1.10 GHz.
Contents
Cache
- Main article: Coffee Lake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
Memory controller
Integrated Memory Controller
|
||||||||||||||
|
Expansions
Expansion Options |
|||||
|
Graphics
Facts about "Core i5-8500B - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i5-8500B - Intel#pcie + |
base frequency | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
clock multiplier | 30 + |
core count | 6 + |
core name | Coffee Lake S + |
designer | Intel + |
die area | 126 mm² (0.195 in², 1.26 cm², 126,000,000 µm²) + |
family | Core i5 + |
first announced | April 2, 2018 + |
first launched | April 2, 2018 + |
full page name | intel/core i5/i5-8500b + |
has ecc memory support | false + |
has locked clock multiplier | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 386 KiB (395,264 B, 0.377 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) + |
l3$ description | 12-way set associative + |
l3$ size | 9 MiB (9,216 KiB, 9,437,184 B, 0.00879 GiB) + |
ldate | April 2, 2018 + |
main image | + |
manufacturer | Intel + |
market segment | Mobile + |
max cpu count | 1 + |
max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) + |
max memory bandwidth | 39.74 GiB/s (40,693.76 MiB/s, 42.671 GB/s, 42,670.5 MB/s, 0.0388 TiB/s, 0.0427 TB/s) + |
max memory channels | 2 + |
microarchitecture | Coffee Lake + |
model number | i5-8500B + |
name | Core i5-8500B + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
series | i5-8000 + |
smp max ways | 1 + |
supported memory type | DDR4-2666 + |
technology | CMOS + |
thread count | 6 + |
turbo frequency (1 core) | 4,100 MHz (4.1 GHz, 4,100,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |