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Difference between revisions of "amd/epyc embedded/3451"
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== Expansions ==
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The EPYC Embedded 3451 has 64 PCIe lanes that are MUX'ed with a number of other ports and can be reconfigured as either SATA ports (up to 16 such ports), or as GbE ports (up to 10 such ports), or any mixed configuration of those options.
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{{expansions main
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{{expansions entry
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|type=PCIe
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|pcie revision=3.0
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|pcie lanes=64
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|pcie config=x16
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|pcie config 2=x8
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|pcie config 3=x4
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|pcie config 4=x2
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}}
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}}

Revision as of 15:57, 22 February 2018

Edit Values
EPYC Embedded 3451
General Info
DesignerAMD
ManufacturerGlobalFoundries
Model Number3451
MarketServer, Embedded
IntroductionFebruary 21, 2018 (announced)
February 21, 2018 (launched)
Release Price$880
ShopAmazon
General Specs
FamilyEPYC Embedded
Series3000
Frequency2,150 MHz
Turbo Frequency3,000 MHz (1 core)
Clock multiplier21.5
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureZen
Core NameSnowy Owl
Process14 nm
Transistors9,600,000,000
TechnologyCMOS
Die213 mm²
MCPYes (2 dies)
Word Size64 bit
Cores16
Threads32
Max Memory1 TiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP100 W
Tjunction0 °C – 95 °C
Packaging
Template:packages/amd/package sp4

EPYC Embedded 3451 is a 64-bit hexadeca-core x86 embedded microprocessor introduced by AMD in early 2018 for dense servers and edge devices. Fabricated on a 14 nm process based on the Zen microarchitecture, this chip operates at 2.15 GHz with a TDP of 100 W and a turbo frequency of up to 3 GHz. The 3451 supports up to 1 TiB of quad-channel DDR4-2666 ECC memory.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache

Main article: Zen § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.5 MiB
1,536 KiB
1,572,864 B
L1I$1 MiB
1,024 KiB
1,048,576 B
16x64 KiB4-way set associative 
L1D$512 KiB
524,288 B
0.5 MiB
16x32 KiB8-way set associativewrite-back
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  16x512 KiB8-way set associativewrite-back
L3$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  4x8 MiB16-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem1 TiB
Controllers4
Channels4
Max Bandwidth79.47 GiB/s
81,377.28 MiB/s
85.33 GB/s
85,330.263 MB/s
0.0776 TiB/s
0.0853 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
[Edit] Official AMD Supported Memory Configurations
Quad Channel Single Rank 1 DIMM per channel 4 of 8 DDR4-2666
2 DIMMs per channel 8 of 8 DDR4-2133
Dual Rank 1 DIMM per channel 4 of 8 DDR4-2400
2 DIMMs per channel 8 of 8 DDR4-1866

Expansions

The EPYC Embedded 3451 has 64 PCIe lanes that are MUX'ed with a number of other ports and can be reconfigured as either SATA ports (up to 16 such ports), or as GbE ports (up to 10 such ports), or any mixed configuration of those options.

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 64
Configuration: x16, x8, x4, x2
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/epyc_embedded/3451&oldid=74379"
Facts about "EPYC Embedded 3451 - AMD"
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EPYC Embedded 3451 - AMD#pcie +
base frequency2,150 MHz (2.15 GHz, 2,150,000 kHz) +
clock multiplier21.5 +
core count16 +
core nameSnowy Owl +
designerAMD +
die area213 mm² (0.33 in², 2.13 cm², 213,000,000 µm²) +
die count2 +
familyEPYC Embedded +
first announcedFebruary 21, 2018 +
first launchedFebruary 21, 2018 +
full page nameamd/epyc embedded/3451 +
has ecc memory supporttrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l1d$ description8-way set associative +
l1d$ size512 KiB (524,288 B, 0.5 MiB) +
l1i$ description4-way set associative +
l1i$ size1,024 KiB (1,048,576 B, 1 MiB) +
l2$ description8-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description16-way set associative +
l3$ size32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldateFebruary 21, 2018 +
manufacturerGlobalFoundries +
market segmentServer + and Embedded +
max cpu count1 +
max junction temperature368.15 K (95 °C, 203 °F, 662.67 °R) +
max memory1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) +
max memory channels4 +
microarchitectureZen +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model number3451 +
nameEPYC Embedded 3451 +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 880.00 (€ 792.00, £ 712.80, ¥ 90,930.40) +
series3000 +
smp max ways1 +
supported memory typeDDR4-2666 +
tdp100 W (100,000 mW, 0.134 hp, 0.1 kW) +
technologyCMOS +
thread count32 +
transistor count9,600,000,000 +
turbo frequency (1 core)3,000 MHz (3 GHz, 3,000,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +