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Difference between revisions of "esperanto/microarchitectures/et-minion"
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{{esperanto title|ET-Minion|arch}} | {{esperanto title|ET-Minion|arch}} | ||
| − | {{microarchitecture}} | + | {{microarchitecture |
| + | |atype=CPU | ||
| + | |name=ET-Minion | ||
| + | |designer=Esperanto | ||
| + | |manufacturer=TSMC | ||
| + | |introduction=2018 | ||
| + | |process=7 nm | ||
| + | |type=Superscalar | ||
| + | |type 2=Pipelined | ||
| + | |oooe=No | ||
| + | |speculative=Yes | ||
| + | |renaming=No | ||
| + | |isa=RV64 | ||
| + | |extension=I | ||
| + | |extension 2=M | ||
| + | |extension 3=A | ||
| + | |extension 4=F | ||
| + | |extension 5=D | ||
| + | |extension 6=C | ||
| + | |contemporary=ET-Maxion | ||
| + | |contemporary link=esperanto/microarchitectures/et-maxion | ||
| + | }} | ||
| + | '''ET-Minion''' is an energy-efficient [[RISC-V]] microarchitecture designed by [[Esperanto]]. ET-Minion is also sold as a licensable [[IP core]]. | ||
| + | |||
| + | == Process Technology == | ||
| + | ET-Minion is designed and optimized for [[TSMC]]'s [[7 nm process]] although it may be back-ported to older nodes in the future. | ||
| + | |||
| + | == Architecture == | ||
| + | {{future information}} | ||
| + | ET-Minion is designed to deliver the best TeraFLOP per Watt efficiency. That is, this core was designed to achieve the highest floating point throughput with a high degree of energy efficiency. | ||
| + | |||
| + | * In-order pipeline | ||
| + | ** Multi-thread | ||
| + | * Integrated vector floating point unit | ||
| + | ** Extension for Tensor instructions | ||
| + | ** Extension for graphics operations | ||
| + | * Support for hardware accelerators | ||
| + | === Block Diagram === | ||
| + | {{empty section}} | ||
| + | |||
| + | === Memory Hierarchy === | ||
| + | {{empty section}} | ||
Latest revision as of 04:58, 9 February 2018
| Edit Values | |
| ET-Minion µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Esperanto |
| Manufacturer | TSMC |
| Introduction | 2018 |
| Process | 7 nm |
| Pipeline | |
| Type | Superscalar, Pipelined |
| OoOE | No |
| Speculative | Yes |
| Reg Renaming | No |
| Instructions | |
| ISA | RV64 |
| Extensions | I, M, A, F, D, C |
| Contemporary | |
| ET-Maxion | |
ET-Minion is an energy-efficient RISC-V microarchitecture designed by Esperanto. ET-Minion is also sold as a licensable IP core.
Process Technology[edit]
ET-Minion is designed and optimized for TSMC's 7 nm process although it may be back-ported to older nodes in the future.
Architecture[edit]
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
ET-Minion is designed to deliver the best TeraFLOP per Watt efficiency. That is, this core was designed to achieve the highest floating point throughput with a high degree of energy efficiency.
- In-order pipeline
- Multi-thread
- Integrated vector floating point unit
- Extension for Tensor instructions
- Extension for graphics operations
- Support for hardware accelerators
Block Diagram[edit]
 |
This section is empty; you can help add the missing info by editing this page. |
Memory Hierarchy[edit]
| |
This section is empty; you can help add the missing info by editing this page. |
Facts about "ET-Minion - Microarchitectures - Esperanto"
| codename | ET-Minion + |
| designer | Esperanto + |
| first launched | 2018 + |
| full page name | esperanto/microarchitectures/et-minion + |
| instance of | microarchitecture + |
| instruction set architecture | RV64 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | ET-Minion + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) + |