From WikiChip
Difference between revisions of "intel/xeon d/d-2146nt"
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{{intel title|Xeon D-2146NT}} | {{intel title|Xeon D-2146NT}} | ||
{{chip | {{chip | ||
− | |||
|name=Xeon D-2146NT | |name=Xeon D-2146NT | ||
− | | | + | |image=skylake-de (front).png |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=D-2146NT | |model number=D-2146NT | ||
+ | |part number=FH8067303782601 | ||
+ | |s-spec=SR3ZR | ||
|market=Server | |market=Server | ||
|market 2=Embedded | |market 2=Embedded | ||
+ | |release price=$641.00 | ||
|family=Xeon D | |family=Xeon D | ||
|series=D-2000 | |series=D-2000 | ||
|locked=Yes | |locked=Yes | ||
+ | |frequency=2,300 MHz | ||
+ | |turbo frequency1=3,000 MHz | ||
+ | |bus type=DMI 3.0 | ||
+ | |bus links=4 | ||
+ | |bus rate=8 GT/s | ||
+ | |clock multiplier=23 | ||
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
|microarch=Skylake (server) | |microarch=Skylake (server) | ||
− | |core name=Skylake- | + | |core name=Skylake-DE |
+ | |core stepping=M1 | ||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
+ | |mcp=Yes | ||
+ | |die count=2 | ||
|word size=64 bit | |word size=64 bit | ||
|core count=8 | |core count=8 | ||
Line 23: | Line 34: | ||
|max cpus=1 | |max cpus=1 | ||
|max memory=512 GiB | |max memory=512 GiB | ||
+ | |tdp=80 W | ||
}} | }} | ||
'''Xeon D-2146NT''' is a {{arch|64}} [[octa-core]] high-performance [[x86]] microserver processor set to be introduced by [[Intel]] in early [[2018]]. Fabricated on Intel's [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|l=arch|Skylake microarchitecture}}, this chip operates at ? GHz with a [[TDP]] of ? W. | '''Xeon D-2146NT''' is a {{arch|64}} [[octa-core]] high-performance [[x86]] microserver processor set to be introduced by [[Intel]] in early [[2018]]. Fabricated on Intel's [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|l=arch|Skylake microarchitecture}}, this chip operates at ? GHz with a [[TDP]] of ? W. |
Revision as of 14:12, 7 February 2018
Edit Values | |
Xeon D-2146NT | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | D-2146NT |
Part Number | FH8067303782601 |
S-Spec | SR3ZR |
Market | Server, Embedded |
Release Price | $641.00 |
Shop | Amazon |
General Specs | |
Family | Xeon D |
Series | D-2000 |
Locked | Yes |
Frequency | 2,300 MHz |
Turbo Frequency | 3,000 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 23 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Core Name | Skylake-DE |
Core Stepping | M1 |
Process | 14 nm |
Technology | CMOS |
MCP | Yes (2 dies) |
Word Size | 64 bit |
Cores | 8 |
Threads | 16 |
Max Memory | 512 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 80 W |
Xeon D-2146NT is a 64-bit octa-core high-performance x86 microserver processor set to be introduced by Intel in early 2018. Fabricated on Intel's 14nm+ process based on the Skylake microarchitecture, this chip operates at ? GHz with a TDP of ? W.
Contents
Cache
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options |
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Features
[Edit/Modify Supported Features]
Facts about "Xeon D-2146NT - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon D-2146NT - Intel#pcie + |
base frequency | 2,300 MHz (2.3 GHz, 2,300,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
clock multiplier | 23 + |
core count | 8 + |
core name | Skylake-DE + |
core stepping | M1 + |
designer | Intel + |
die count | 2 + |
family | Xeon D + |
full page name | intel/xeon d/d-2146nt + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard + and Identity Protection Technology + |
has intel enhanced speedstep technology | true + |
has intel identity protection technology support | true + |
has intel secure key technology | true + |
has intel speed shift technology | true + |
has intel supervisor mode execution protection | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
is multi-chip package | true + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 11 MiB (11,264 KiB, 11,534,336 B, 0.0107 GiB) + |
ldate | 1900 + |
main image | + |
manufacturer | Intel + |
market segment | Server + and Embedded + |
max cpu count | 1 + |
max memory | 524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) + |
max memory bandwidth | 79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) + |
max memory channels | 4 + |
microarchitecture | Skylake (server) + |
model number | D-2146NT + |
name | Xeon D-2146NT + |
number of avx-512 execution units | 2 + |
part number | FH8067303782601 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 641.00 (€ 576.90, £ 519.21, ¥ 66,234.53) + |
s-spec | SR3ZR + |
series | D-2000 + |
smp max ways | 1 + |
supported memory type | DDR4-2666 + |
tdp | 80 W (80,000 mW, 0.107 hp, 0.08 kW) + |
technology | CMOS + |
thread count | 16 + |
turbo frequency (1 core) | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |
x86/has memory protection extensions | true + |