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Difference between revisions of "zhaoxin/kaixian/kx-u5580m"
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Revision as of 01:21, 31 January 2018

Edit Values
KaiXian KX-U5580M
KX-U5580M.png
KX-U5580M front
General Info
DesignerZhaoxin
ManufacturerHLMC
Model NumberKX-U5580M
Part NumberKX-U5580M
MarketDesktop, Mobile, Embedded
IntroductionDecember 28, 2017 (announced)
December 28, 2017 (launched)
General Specs
FamilyKaiXian
SeriesKX-5000
Frequency1,800 MHz
Bus typePCIe 3.0
Bus rate4 × 8 GT/s
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureWuDaoKou
Process28 nm
Transistors2,100,000,000
TechnologyCMOS
Die187 mm²
Word Size64 bit
Cores8
Threads8
Max Memory64 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Tjunction0 °C – 90 °C

KaiXian KX-U5580M is a 64-bit octa-core x86 microprocessor designed by Zhaoxin and introduced in late 2017 specifically for the Chinese market. This processor is fabricated on a 28 nm process based on the WuDaoKou microarchitecture. The KX-U5580M operates at 1.8 GHz with a TDP of ? W and supports up to 64 GiB of dual-channel DDR4-2133 memory. The KX-U5580M also incorporates an integrated graphics processor.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache

Main article: WuDaoKou § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  2x4 MiB32-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133
Supports ECCNo
Max Mem64 GiB
Controllers1
Channels2
Max Bandwidth31.79 GiB/s
32,552.96 MiB/s
34.134 GB/s
34,134.253 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 24


Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPU?
DesignerZhaoxin
Max Displays3
Frequency? MHz
"? MHz" is not a number.
OutputDP, eDP, HDMI, VGA
Max Resolution
HDMI4096x2304
DP4096x2304 @60 Hz
eDP4096x2304 @60 Hz
Standards
DirectX11.1
DP1.2a
eDP1.3
HDMI1.4b

Features

Retrieved from "https://en.wikichip.org/w/index.php?title=zhaoxin/kaixian/kx-u5580m&oldid=73313"
Facts about "KaiXian KX-U5580M - Zhaoxin"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
KaiXian KX-U5580M - Zhaoxin#pcie +
base frequency1,800 MHz (1.8 GHz, 1,800,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typePCIe 3.0 +
core count8 +
designerZhaoxin +
die area187 mm² (0.29 in², 1.87 cm², 187,000,000 µm²) +
familyKaiXian +
first announcedDecember 28, 2017 +
first launchedDecember 28, 2017 +
full page namezhaoxin/kaixian/kx-u5580m +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has ecc memory supportfalse +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Trusted Execution Technology +, Intel VT-x + and Extended Page Tables +
has intel trusted execution technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
integrated gpu? +
integrated gpu designerZhaoxin +
isax86-64 +
isa familyx86 +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description32-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
ldateDecember 28, 2017 +
main imageFile:KX-U5580M.png +
main image captionKX-U5580M front +
manufacturerHLMC +
market segmentDesktop +, Mobile + and Embedded +
max cpu count1 +
max junction temperature363.15 K (90 °C, 194 °F, 653.67 °R) +
max memory65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
max memory bandwidth31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels2 +
microarchitectureWuDaoKou +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model numberKX-U5580M +
nameKaiXian KX-U5580M +
part numberKX-U5580M +
process28 nm (0.028 μm, 2.8e-5 mm) +
seriesKX-5000 +
smp max ways1 +
supported memory typeDDR4-2133 +
technologyCMOS +
thread count8 +
transistor count2,100,000,000 +
word size64 bit (8 octets, 16 nibbles) +