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Difference between revisions of "zhaoxin/microarchitectures/zhangjiang"
< zhaoxin
| Line 2: | Line 2: | ||
{{microarchitecture | {{microarchitecture | ||
|atype=CPU | |atype=CPU | ||
| − | |name= | + | |name=ZhangJiang |
|designer=Zhaoxin | |designer=Zhaoxin | ||
|manufacturer=TSMC | |manufacturer=TSMC | ||
Revision as of 21:34, 14 January 2018
| Edit Values | |
| ZhangJiang µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Zhaoxin |
| Manufacturer | TSMC |
| Introduction | 2015 |
| Process | 28 nm |
| Core Configs | 2, 4, 8 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | x86-64 |
| Succession | |
ZhangJiang is the successor to Isaiah II, a 28 nm x86 microarchitecture designed by Zhaoxin for mainstream laptops, desktops, and servers.
Retrieved from "https://en.wikichip.org/w/index.php?title=zhaoxin/microarchitectures/zhangjiang&oldid=72529"
Facts about "ZhangJiang - Microarchitectures - Zhaoxin"
| codename | ZhangJiang + |
| core count | 2 +, 4 + and 8 + |
| designer | Zhaoxin + |
| first launched | 2015 + |
| full page name | zhaoxin/microarchitectures/zhangjiang + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | ZhangJiang + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) + |