From WikiChip
Difference between revisions of "zhaoxin/microarchitectures/zhangjiang"
| Line 15: | Line 15: | ||
|renaming=Yes | |renaming=Yes | ||
|isa=x86-64 | |isa=x86-64 | ||
| − | |predecessor=Isaiah | + | |predecessor=Isaiah II |
| − | |predecessor link=via_technologies/microarchitectures/isaiah | + | |predecessor link=via_technologies/microarchitectures/isaiah ii |
|successor=WuDaoKou | |successor=WuDaoKou | ||
|successor link=zhaoxin/microarchitectures/wudaokou | |successor link=zhaoxin/microarchitectures/wudaokou | ||
}} | }} | ||
| − | '''ZhangJiang''' is the successor to {{via|Isaiah|l=arch}}, a [[28 nm]] [[x86]] microarchitecture designed by [[Zhaoxin]] for mainstream laptops, desktops, and servers. | + | '''ZhangJiang''' is the successor to {{via|Isaiah II|l=arch}}, a [[28 nm]] [[x86]] microarchitecture designed by [[Zhaoxin]] for mainstream laptops, desktops, and servers. |
Revision as of 21:33, 14 January 2018
| Edit Values | |
| WuDaoKou µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Zhaoxin |
| Manufacturer | TSMC |
| Introduction | 2015 |
| Process | 28 nm |
| Core Configs | 2, 4, 8 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | x86-64 |
| Succession | |
ZhangJiang is the successor to Isaiah II, a 28 nm x86 microarchitecture designed by Zhaoxin for mainstream laptops, desktops, and servers.
Facts about "ZhangJiang - Microarchitectures - Zhaoxin"
| codename | WuDaoKou + |
| core count | 2 +, 4 + and 8 + |
| designer | Zhaoxin + |
| first launched | 2015 + |
| full page name | zhaoxin/microarchitectures/zhangjiang + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | WuDaoKou + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) + |