Semiconductor & Computer Engineering
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Difference between revisions of "loongson/godson 2/2b1"
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| name = Godson-2B1 | | name = Godson-2B1 | ||
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| model number = 2B1 | | model number = 2B1 | ||
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| market = Desktop | | market = Desktop | ||
| first announced = 2004 | | first announced = 2004 | ||
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| power = 4 W | | power = 4 W | ||
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Latest revision as of 16:31, 13 December 2017
| Edit Values | |
| Godson-2B1 | |
| General Info | |
| Designer | Loongson |
| Manufacturer | SMICS |
| Model Number | 2B1 |
| Market | Desktop |
| Introduction | 2004 (announced) March, 2004 (launched) |
| General Specs | |
| Family | Godson 2 |
| Series | Godson 2 |
| Frequency | 400 MHz |
| Microarchitecture | |
| ISA | MIPS64 (MIPS) |
| Microarchitecture | GS464 |
| Core Name | GS464 |
| Process | 180 nm |
| Technology | CMOS |
| Word Size | 64 bit |
| Cores | 1 |
| Threads | 1 |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Power dissipation | 4 W |
Godson-2B1 (龙芯2B1) is a 64-bit MIPS performance processor developed by ICT and later Loongson for desktop computers. Introduced in early 2004, the Godson-2B1 operates at up to 400 MHz consuming up to 4 W. This chip was manufactured on SMICS' 0.18 µm process. This chip reached tapeout on March 7, 2004.
The Godson-2B1 is roughly twice the performance of the 2B.
Cache[edit]
- Main article: GS464 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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