Semiconductor & Computer Engineering
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Difference between revisions of "intel/atom x3/x3-c3230rk"
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{{intel title|Atom x3-C3230RK}} | {{intel title|Atom x3-C3230RK}} | ||
| − | {{ | + | {{chip |
| name = Atom x3-C3230RK | | name = Atom x3-C3230RK | ||
| no image = Yes | | no image = Yes | ||
| image = | | image = | ||
| caption = | | caption = | ||
| − | | manufacturer = | + | | designer = Intel |
| + | | manufacturer = TSMC | ||
| model number = x3-C3230RK | | model number = x3-C3230RK | ||
| part number = | | part number = | ||
| Line 39: | Line 40: | ||
| thread count = 4 | | thread count = 4 | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = | + | | max memory = 2 GiB |
| + | |||
| − | |||
| power = | | power = | ||
| sdp = 2 W | | sdp = 2 W | ||
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== Cache == | == Cache == | ||
{{cache info | {{cache info | ||
| − | + | |l2 cache=2 MiB | |
| − | + | |l2 break=2x1 MiB | |
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |l2 cache=2 | ||
| − | |l2 break=2x1 | ||
| − | |||
|l2 extra=(per 2 cores) | |l2 extra=(per 2 cores) | ||
| − | |l3 cache=0 | + | |l3 cache=0 KiB |
|l3 desc=No L3$ | |l3 desc=No L3$ | ||
}} | }} | ||
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== Features == | == Features == | ||
| − | {{ | + | {{x86 features |
| em64t = Yes | | em64t = Yes | ||
| nx = Yes | | nx = Yes | ||
Latest revision as of 15:15, 13 December 2017
| Edit Values | |
| Atom x3-C3230RK | |
| General Info | |
| Designer | Intel |
| Manufacturer | TSMC |
| Model Number | x3-C3230RK |
| Market | Mobile |
| Introduction | March 4, 2015 (announced) March 4, 2015 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | Atom x3 |
| Series | C3000 |
| Locked | Yes |
| Frequency | 1100 MHz |
| Microarchitecture | |
| Microarchitecture | Silvermont |
| Platform | SoFIA |
| Core Name | SoFIA |
| Process | 28 nm |
| Technology | CMOS |
| Word Size | 64 bit |
| Cores | 4 |
| Threads | 4 |
| Max Memory | 2 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| SDP | 2 W |
| OP Temperature | -25 °C – 85 °C |
The x3-C3230RK is a quad-core 64-bit system-on-chip designed by Intel and introduced in March 2015. The x3-C3230RK is one of thee first of Intel's SoC to integrate a 3G modem. This chip operates at 1.1 GHz and manufactured in 28 nm process designed for entry-level smart phones. This SoC integrates an Arm Mali-450 MP4 GPU.
The x3-C3200RK is a WiFi-only identical version of this chip.
Contents
Cache[edit]
| Cache Info [Edit Values] | ||
| L2$ | 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB |
2x1 MiB (per 2 cores) |
| L3$ | 0 KiB 0 MiB 0 B 0 GiB |
No L3$ |
Graphics[edit]
| Integrated Graphic Information | |
| GPU | Mali-450 MP4 |
| Displays | 1 |
| Frequency | 600 MHz 0.6 GHz
600,000 KHz |
| Output | DSI |
| OpenGL ES | 2.0 |
| Max DSI Res | 1920x1080 @60 Hz |
Memory controller[edit]
| Integrated Memory Controller | |
| Type | LPDDR2-1066, LPDDR3-1066, DDR3L-1333 |
| Controllers | 1 |
| Channels | 1 |
| ECC Support | No |
| Max bandwidth | 4,200 MB/s |
| Max memory | 2,048 MB |
Input/Output[edit]
- USB Revision: 2.0 OTG
- USB Ports: 1
- GP I/O: 4x I2C
- UART: 2x USIF
- GLONASS
Storage[edit]
- eMMC 4.51
Features[edit]
[Edit/Modify Supported Features]
 |
Supported x86 Extensions & Processor Features
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Networking[edit]
- RF Transceiver: A-GOLD 620
- Baseband Functions: HSDPA+ 21Mbps HSUPA 5.8 Mbps, GSM/GPRS/EDGE, DSDS
- RF Transceiver Functions: Low power multimode multiband transceiver for 3G 2.5G 2G
- Wi-Fi: 802.11 B/G/N
- Bluetooth: 4.0 LE
- GPS & GLONASS
- FM Radio
- Protocol Stack: Intel Release 9 Protocol Stack
ISP/Camera[edit]
- Up to 13 MP/5 MP
Facts about "Atom x3-C3230RK - Intel"
| has feature | integrated gpu + |
| integrated gpu | Mali-450 MP4 + |
| integrated gpu base frequency | 600 MHz (0.6 GHz, 600,000 KHz) + |
| l3$ description | No L3$ + |
| l3$ size | 0 MiB (0 KiB, 0 B, 0 GiB) + |