From WikiChip
Difference between revisions of "intel/microarchitectures/goldmont plus"
< intel‎ | microarchitectures

(https://newsroom.intel.com/news/introducing-new-intel-pentium-silver-intel-celeron-processors/)
(brands)
Line 47: Line 47:
 
! Platform !! Core !! Target
 
! Platform !! Core !! Target
 
|-
 
|-
−
| {{intel|Gemini Lake}} || {{intel|Gemini Lake|l=core}} || Entry-level PCs, Communications, Storage, Tablets
+
| {{intel|Gemini Lake}} || {{intel|Gemini Lake|l=core}} || Entry-level PCs, tablets, embedded devices, storage
 +
|}
 +
 
 +
== Brands ==
 +
Intel released Goldmont Plus under 2 main brand families:
 +
 
 +
{| class="wikitable tc4 tc5 tc6 tc7 tc8"
 +
|-
 +
! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="7" | Differentiating Features
 +
|-
 +
! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AES}} !! {{x86|SHA}} !! {{x86|AVX}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]
 +
|-
 +
| [[File:intel celeron (2015).png|50px|link=intel/celeron]] || {{intel|Celeron}} || style="text-align: left;" | Entry-level Budget || [[2 cores|2]]-[[4 cores|4]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}}
 +
|-
 +
| rowspan="2" | [[File:intel pentium silver logo (2017).png|50px|link=intel/pentium_silver]] || rowspan="2" | {{intel|Pentium Silver}} || style="text-align: left;" | Budget || rowspan="2" | [[4 cores|4]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}}
 
|}
 
|}
  

Revision as of 14:48, 11 December 2017

Edit Values
Goldmont Plus µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionDecember 11, 2017
Process14 nm
Core Configs2, 4
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, SHA
Cache
L1I Cache32 KiB/Core
8-way set associative
L1D Cache24 KiB/Core
6-way set associative
L2 Cache2 MiB/2 Cores
16-way set associative
Cores
Core NamesGemini Lake
Succession

Goldmont Plus (GLM+) is Intel's 14 nm microarchitecture of system on chips for the ultra-low power (ULP) devices serving as a successor to Goldmont. Goldmont Plus-based processors and SoCs are part of the Atom, Pentium, and Celeron families.

Codenames

Platform Core Target
Gemini Lake Gemini Lake Entry-level PCs, tablets, embedded devices, storage

Brands

Intel released Goldmont Plus under 2 main brand families:

Logo Family General Description Differentiating Features
Cores HT AES SHA AVX TBT ECC
intel celeron (2015).png Celeron Entry-level Budget 2-4 ✘ ✔ ✔ ✘ ✘ ✘
intel pentium silver logo (2017).png Pentium Silver Budget 4 ✘ ✔ ✔ ✘ ✘ ✘

Architecture

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Key changes from Goldmont

  • 4-way decode (from 3-way)[1]
  • VP9 10-bit Profile2 hardware decoding
  • Integrated native HDMI 2.0 controller
  • Integrated Intel Wireless-AC(Wi-Fi/BT CNVi)
  • 4 MiB L2 cache per duplex (Up from 2 MiB)

New instructions

Goldmont Plus introduced a number of new instructions:

  • SGX1 - Software Guard Extensions, Version 1
  • UMIP
  • PTWRITE
  • RDPID

Block Diagram

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory Hierarchy

  • Cache
    • Hardware prefetchers
    • L1 Cache:
      • 32 KiB 8-way set associative instruction, 64 B line size
      • 24 KiB 6-way set associative data, 64 B line size
      • Per core
    • L2 Cache:
      • 4 MiB 16-way set associative, 64 B line size
      • Per 2 cores
    • L3 Cache:
      • No level 3 cache
    • RAM
      • Maximum of 1 GiB, 2 GiB, 4 GiB, 8 GiB
      • dual 32-bit channels, 1 or 2 ranks per channel

Multithreading

Goldmont Plus, like Goldmont has no support for Intel Hyper-Threading Technology.

Core

New text document.svg This section is empty; you can help add the missing info by editing this page.
  1. ↑ https://patchwork.kernel.org/patch/9836747/
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/goldmont_plus&oldid=69025"
Facts about "Goldmont Plus - Microarchitectures - Intel"
RDF feed
codenameGoldmont Plus +
core count2 + and 4 +
designerIntel +
first launchedDecember 11, 2017 +
full page nameintel/microarchitectures/goldmont plus +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameGoldmont Plus +
process14 nm (0.014 μm, 1.4e-5 mm) +