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Difference between revisions of "intel/microarchitectures/goldmont plus"
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! Platform !! Core !! Target | ! Platform !! Core !! Target | ||
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− | | {{intel|Gemini Lake}} || {{intel|Gemini Lake|l=core}} || Entry-level PCs, | + | | {{intel|Gemini Lake}} || {{intel|Gemini Lake|l=core}} || Entry-level PCs, tablets, embedded devices, storage |
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+ | == Brands == | ||
+ | Intel released Goldmont Plus under 2 main brand families: | ||
+ | |||
+ | {| class="wikitable tc4 tc5 tc6 tc7 tc8" | ||
+ | |- | ||
+ | ! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="7" | Differentiating Features | ||
+ | |- | ||
+ | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AES}} !! {{x86|SHA}} !! {{x86|AVX}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]] | ||
+ | |- | ||
+ | | [[File:intel celeron (2015).png|50px|link=intel/celeron]] || {{intel|Celeron}} || style="text-align: left;" | Entry-level Budget || [[2 cores|2]]-[[4 cores|4]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} | ||
+ | |- | ||
+ | | rowspan="2" | [[File:intel pentium silver logo (2017).png|50px|link=intel/pentium_silver]] || rowspan="2" | {{intel|Pentium Silver}} || style="text-align: left;" | Budget || rowspan="2" | [[4 cores|4]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} | ||
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Revision as of 15:48, 11 December 2017
Edit Values | |
Goldmont Plus µarch | |
General Info | |
Arch Type | CPU |
Designer | Intel |
Manufacturer | Intel |
Introduction | December 11, 2017 |
Process | 14 nm |
Core Configs | 2, 4 |
Pipeline | |
Type | Superscalar |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Instructions | |
ISA | x86-64 |
Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, SHA |
Cache | |
L1I Cache | 32 KiB/Core 8-way set associative |
L1D Cache | 24 KiB/Core 6-way set associative |
L2 Cache | 2 MiB/2 Cores 16-way set associative |
Cores | |
Core Names | Gemini Lake |
Succession | |
Goldmont Plus (GLM+) is Intel's 14 nm microarchitecture of system on chips for the ultra-low power (ULP) devices serving as a successor to Goldmont. Goldmont Plus-based processors and SoCs are part of the Atom, Pentium, and Celeron families.
Contents
Codenames
Platform | Core | Target |
---|---|---|
Gemini Lake | Gemini Lake | Entry-level PCs, tablets, embedded devices, storage |
Brands
Intel released Goldmont Plus under 2 main brand families:
Logo | Family | General Description | Differentiating Features | ||||||
---|---|---|---|---|---|---|---|---|---|
Cores | HT | AES | SHA | AVX | TBT | ECC | |||
![]() |
Celeron | Entry-level Budget | 2-4 | ✘ | ✔ | ✔ | ✘ | ✘ | ✘ |
![]() |
Pentium Silver | Budget | 4 | ✘ | ✔ | ✔ | ✘ | ✘ | ✘ |
Architecture
Key changes from Goldmont
- 4-way decode (from 3-way)[1]
- VP9 10-bit Profile2 hardware decoding
- Integrated native HDMI 2.0 controller
- Integrated Intel Wireless-AC(Wi-Fi/BT CNVi)
- 4 MiB L2 cache per duplex (Up from 2 MiB)
- Graphics
- Gen 9.5 GPUs
- HD Graphics 50x → UHD Graphics 60x
- HD Graphics 505 → UHD Graphics 605 (Pentium Silver J/N 5xxx with 18EU)
- HD Graphics 500 → UHD Graphics 600 (Celeron J/N 4xxx with 12EU)
New instructions
Goldmont Plus introduced a number of new instructions:
-
SGX1
- Software Guard Extensions, Version 1 - UMIP
- PTWRITE
- RDPID
Block Diagram
![]() |
This section is empty; you can help add the missing info by editing this page. |
Memory Hierarchy
- Cache
- Hardware prefetchers
- L1 Cache:
- 32 KiB 8-way set associative instruction, 64 B line size
- 24 KiB 6-way set associative data, 64 B line size
- Per core
- L2 Cache:
- 4 MiB 16-way set associative, 64 B line size
- Per 2 cores
- L3 Cache:
- No level 3 cache
- RAM
- Maximum of 1 GiB, 2 GiB, 4 GiB, 8 GiB
- dual 32-bit channels, 1 or 2 ranks per channel
Multithreading
Goldmont Plus, like Goldmont has no support for Intel Hyper-Threading Technology.
Core
![]() |
This section is empty; you can help add the missing info by editing this page. |
Facts about "Goldmont Plus - Microarchitectures - Intel"
codename | Goldmont Plus + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | December 11, 2017 + |
full page name | intel/microarchitectures/goldmont plus + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Goldmont Plus + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |