Semiconductor & Computer Engineering
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- 15:10, 13 December 2017 (diff | hist) . . (-82) . . intel/microarchitectures/goldmont plus (https://www.anandtech.com/show/12146/intel-launches-gemini-lake-pentium-silver-and-celeron-socs-new-cpu-media-features "Intel also confirmed the microarchitecture is a three-wide decode, the same as Goldmont" Removing 4 way decode for now)
- 11:22, 11 December 2017 (diff | hist) . . (+2) . . intel/microarchitectures/goldmont plus (https://newsroom.intel.com/news/introducing-new-intel-pentium-silver-intel-celeron-processors/)
- 11:21, 11 December 2017 (diff | hist) . . (+4) . . intel/cores/gemini lake (https://newsroom.intel.com/news/introducing-new-intel-pentium-silver-intel-celeron-processors/)
- 13:51, 4 December 2017 (diff | hist) . . (-1) . . intel/microarchitectures/goldmont plus (https://pbs.twimg.com/media/DQMp5DQXUAIXG9T.jpg New Intel roadmap shows December launch for Gemini Lake)
- 13:50, 4 December 2017 (diff | hist) . . (0) . . intel/cores/gemini lake (https://pbs.twimg.com/media/DQMp5DQXUAIXG9T.jpg New Intel roadmap shows December launch for Gemini Lake)
- 06:20, 2 December 2017 (diff | hist) . . (+233) . . intel/microarchitectures/ice lake (client) (https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf Page 13 lists new instructions supported by Ice Lake)
