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Difference between revisions of "intel/microarchitectures/goldmont plus"
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'''Goldmont Plus''' is [[Intel]]'s [[14 nm]] [[microarchitecture]] of [[system on chip]]s for the ultra-low power (ULP) devices serving as a successor to {{\\|Goldmont}}. Goldmont Plus-based processors and SoCs are part of the {{intel|Atom}}, {{intel|Pentium (2009)|Pentium}}, and {{intel|Celeron}} families. | '''Goldmont Plus''' is [[Intel]]'s [[14 nm]] [[microarchitecture]] of [[system on chip]]s for the ultra-low power (ULP) devices serving as a successor to {{\\|Goldmont}}. Goldmont Plus-based processors and SoCs are part of the {{intel|Atom}}, {{intel|Pentium (2009)|Pentium}}, and {{intel|Celeron}} families. | ||
| + | |||
| + | == Codenames == | ||
| + | {| class="wikitable" | ||
| + | |- | ||
| + | ! Platform !! Core !! Target | ||
| + | |- | ||
| + | | {{intel|Gemini Lake}} || {{intel|Gemini Lake|l=core}} || Tablets, Entry-level PCs | ||
| + | |} | ||
== Architecture == | == Architecture == | ||
Revision as of 20:26, 25 July 2017
| Edit Values | |
| Goldmont Plus µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Process | 14 nm |
| Core Configs | 2, 4, 8 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 12-14 |
| Instructions | |
| ISA | IA-32, x86-64 |
| Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, SHA |
| Cache | |
| L1I Cache | 32 KiB/Core 8-way set associative |
| L1D Cache | 24 KiB/Core 6-way set associative |
| L2 Cache | 1 MiB/2 Cores 16-way set associative |
| Cores | |
| Core Names | Apollo Lake |
| Succession | |
Goldmont Plus is Intel's 14 nm microarchitecture of system on chips for the ultra-low power (ULP) devices serving as a successor to Goldmont. Goldmont Plus-based processors and SoCs are part of the Atom, Pentium, and Celeron families.
Codenames
| Platform | Core | Target |
|---|---|---|
| Gemini Lake | Gemini Lake | Tablets, Entry-level PCs |
Architecture
Key changes from Goldmont
- 4-way decode (from 3-way)
Block Diagram
 |
This section is empty; you can help add the missing info by editing this page. |
Core
| |
This section is empty; you can help add the missing info by editing this page. |
Facts about "Goldmont Plus - Microarchitectures - Intel"
| codename | Goldmont Plus + |
| core count | 2 +, 4 + and 8 + |
| designer | Intel + |
| full page name | intel/microarchitectures/goldmont plus + |
| instance of | microarchitecture + |
| instruction set architecture | IA-32 + and x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Goldmont Plus + |
| pipeline stages (max) | 14 + |
| pipeline stages (min) | 12 + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
