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(Created page with "{{intel title|Process Technology}} This article details Intel's Semiconductor Process Technology. == Timeline == <table class="wikitable" style="text-align: center;">...")
 
(→‎Timeline)
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== Timeline ==
 
== Timeline ==
 
<table class="wikitable" style="text-align: center;">
 
<table class="wikitable" style="text-align: center;">
−
<tr><th>Year</th><th>Process Name</th><th>Node Name</th><th>Metal Layers</th><th colspan="4">Attributes</th></tr>
+
<tr><th>Year</th><th>Process Name</th><th>Node Name</th><th>Metal Layers</th><th>µarchs</th><th colspan="4">Attributes</th></tr>
 
{{intel proc tech |year=1982 |name=P646 |mlayers=2 |node=1.5 µm
 
{{intel proc tech |year=1982 |name=P646 |mlayers=2 |node=1.5 µm
 +
  |archs=80286, 80386
 
   |a1=L<sub>g</sub>  |d1=1,500 nm
 
   |a1=L<sub>g</sub>  |d1=1,500 nm
 
   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=Si<sub>2</sub>N<sub>2</sub>O
 
   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=Si<sub>2</sub>N<sub>2</sub>O
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}}
 
}}
 
{{intel proc tech |year=1987 |name=P648 |mlayers=2 |node=1.0 µm
 
{{intel proc tech |year=1987 |name=P648 |mlayers=2 |node=1.0 µm
 +
  |archs=80486
 
   |a1=L<sub>g</sub>  |d1=1,000 nm
 
   |a1=L<sub>g</sub>  |d1=1,000 nm
 
   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=
 
   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=
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}}
 
}}
 
{{intel proc tech |year=1989 |name=P650 |mlayers=3 |node=0.8 µm
 
{{intel proc tech |year=1989 |name=P650 |mlayers=3 |node=0.8 µm
 +
  |archs=80486
 
   |a1=L<sub>g</sub>  |d1=800 nm
 
   |a1=L<sub>g</sub>  |d1=800 nm
 
   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=
 
   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=
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}}
 
}}
 
{{intel proc tech |year=1993 |name=P852 |mlayers=4 |node=0.5 µm
 
{{intel proc tech |year=1993 |name=P852 |mlayers=4 |node=0.5 µm
 +
  |archs=P5
 
   |a1=L<sub>g</sub>  |d1=500 nm
 
   |a1=L<sub>g</sub>  |d1=500 nm
 
   |a2=T<sub>ox</sub> |d2=8.0 nm |a22=Gate Dielectric |d22=
 
   |a2=T<sub>ox</sub> |d2=8.0 nm |a22=Gate Dielectric |d22=
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}}
 
}}
 
{{intel proc tech |year=1995 |name=P854 |mlayers=4 |node=0.35 µm
 
{{intel proc tech |year=1995 |name=P854 |mlayers=4 |node=0.35 µm
 +
  |archs=P6
 
   |a1=L<sub>g</sub>  |d1=350 nm
 
   |a1=L<sub>g</sub>  |d1=350 nm
 
   |a2=T<sub>ox</sub> |d2=5.2 nm |a22=Gate Dielectric |d22=
 
   |a2=T<sub>ox</sub> |d2=5.2 nm |a22=Gate Dielectric |d22=
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}}
 
}}
 
{{intel proc tech |year=1997 |name=P856<br>P856.5 |mlayers=5 |node=0.25 µm
 
{{intel proc tech |year=1997 |name=P856<br>P856.5 |mlayers=5 |node=0.25 µm
 +
  |archs=P6
 
   |a1=L<sub>g</sub>  |d1=200 nm
 
   |a1=L<sub>g</sub>  |d1=200 nm
 
   |a2=T<sub>ox</sub> |d2=3.1 nm |a22=Gate Dielectric |d22=SiO<sub>2</sub>
 
   |a2=T<sub>ox</sub> |d2=3.1 nm |a22=Gate Dielectric |d22=SiO<sub>2</sub>
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}}
 
}}
 
{{intel proc tech |year=1999 |name=P858 |mlayers=6 |node=0.18 µm
 
{{intel proc tech |year=1999 |name=P858 |mlayers=6 |node=0.18 µm
 +
  |archs=NetBurst
 
   |a1=L<sub>g</sub>  |d1=130 nm
 
   |a1=L<sub>g</sub>  |d1=130 nm
 
   |a2=T<sub>ox</sub> |d2=2.0 nm |a22=Gate Dielectric |d22=SiO<sub>2</sub>
 
   |a2=T<sub>ox</sub> |d2=2.0 nm |a22=Gate Dielectric |d22=SiO<sub>2</sub>
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}}
 
}}
 
{{intel proc tech |year=2001 |name=P860 |mlayers=6 |node=0.13 µm
 
{{intel proc tech |year=2001 |name=P860 |mlayers=6 |node=0.13 µm
 +
  |archs=Pentium M
 
   |a1=L<sub>g</sub>  |d1=70 nm
 
   |a1=L<sub>g</sub>  |d1=70 nm
 
   |a2=T<sub>ox</sub> |d2=1.4 nm |a22=Gate Dielectric |d22=SiO<sub>2</sub>
 
   |a2=T<sub>ox</sub> |d2=1.4 nm |a22=Gate Dielectric |d22=SiO<sub>2</sub>
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}}
 
}}
 
{{intel proc tech |year=2003 |name=P1262 |mlayers=7 |node=90 nm
 
{{intel proc tech |year=2003 |name=P1262 |mlayers=7 |node=90 nm
 +
  |archs=Pentium M
 
   |a1=L<sub>g</sub>  |d1=50 nm
 
   |a1=L<sub>g</sub>  |d1=50 nm
 
   |a2=T<sub>ox</sub> |d2=1.2 nm |a22=Gate Dielectric |d22=SiO<sub>2</sub>
 
   |a2=T<sub>ox</sub> |d2=1.2 nm |a22=Gate Dielectric |d22=SiO<sub>2</sub>
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}}
 
}}
 
{{intel proc tech |year=2005 |name=P1264 |mlayers=8 |node=65 nm
 
{{intel proc tech |year=2005 |name=P1264 |mlayers=8 |node=65 nm
 +
  |archs=Core, Modified Pentium M
 
   |a1=L<sub>g</sub>  |d1=35 nm
 
   |a1=L<sub>g</sub>  |d1=35 nm
 
   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=SiO<sub>2</sub>
 
   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=SiO<sub>2</sub>
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}}
 
}}
 
{{intel proc tech |year=2007 |name=P1266 |mlayers=9 |node=45 nm
 
{{intel proc tech |year=2007 |name=P1266 |mlayers=9 |node=45 nm
 +
  |archs=Penryn, Nehalem
 
   |a1=L<sub>g</sub>  |d1=25 nm
 
   |a1=L<sub>g</sub>  |d1=25 nm
 
   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=High-κ
 
   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=High-κ
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}}
 
}}
 
{{intel proc tech |year=2009 |name=P1268 |mlayers=10 |node=32 nm
 
{{intel proc tech |year=2009 |name=P1268 |mlayers=10 |node=32 nm
 +
  |archs=Westmere, Sandy Bridge
 
   |a1=L<sub>g</sub>  |d1=30 nm
 
   |a1=L<sub>g</sub>  |d1=30 nm
 
   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=High-κ
 
   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=High-κ
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}}
 
}}
 
{{intel proc tech |year=2011 |name=P1270 |mlayers=11 |node=22 nm
 
{{intel proc tech |year=2011 |name=P1270 |mlayers=11 |node=22 nm
 +
  |archs=Ivy Bridge, Haswell
 
   |a1=L<sub>g</sub>  |d1=26 nm
 
   |a1=L<sub>g</sub>  |d1=26 nm
 
   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=High-κ
 
   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=High-κ
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}}
 
}}
 
{{intel proc tech |year=2014 |name=P1272 |mlayers=11 |node=14 nm
 
{{intel proc tech |year=2014 |name=P1272 |mlayers=11 |node=14 nm
 +
  |archs=Broadwell, Skylake, Kaby Lake, Coffee Lake
 
   |a1=L<sub>g</sub>  |d1=20 nm
 
   |a1=L<sub>g</sub>  |d1=20 nm
 
   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=High-κ
 
   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=High-κ
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}}
 
}}
 
{{intel proc tech |year=2017 |name=P1274 |mlayers= |node=10 nm
 
{{intel proc tech |year=2017 |name=P1274 |mlayers= |node=10 nm
 +
  |archs=Cannonlake, Icelake, Tigerlake
 
   |a1=L<sub>g</sub>  |d1=18? nm
 
   |a1=L<sub>g</sub>  |d1=18? nm
 
   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=High-κ
 
   |a2=T<sub>ox</sub> |d2=? nm |a22=Gate Dielectric |d22=High-κ

Revision as of 01:29, 11 May 2017

This article details Intel's Semiconductor Process Technology.

Timeline

YearProcess NameNode NameMetal LayersµarchsAttributes
1982 P646 1.5 µm 2 80286,
80386		 Lg1,500 nm
Tox? nmGate DielectricSi2N2O
Vdd? V
1987 P648 1.0 µm 2 80486 Lg1,000 nm
Tox? nmGate Dielectric
Vdd? V
1989 P650 0.8 µm 3 80486 Lg800 nm
Tox? nmGate Dielectric
Vdd? V
1993 P852 0.5 µm 4 P5 Lg500 nm
Tox8.0 nmGate Dielectric
Vdd3.3 V
1995 P854 0.35 µm 4 P6 Lg350 nm
Tox5.2 nmGate Dielectric
Vdd2.5 V
1997 P856
P856.5		 0.25 µm 5 P6 Lg200 nm
Tox3.1 nmGate DielectricSiO2
Vdd1.8 V
1999 P858 0.18 µm 6 NetBurst Lg130 nm
Tox2.0 nmGate DielectricSiO2
Vdd1.6 V
2001 P860 0.13 µm 6 Pentium M Lg70 nm
Tox1.4 nmGate DielectricSiO2
Vdd1.4 V
2003 P1262 90 nm 7 Pentium M Lg50 nm
Tox1.2 nmGate DielectricSiO2
Vdd1.2 V
2005 P1264 65 nm 8 Core,
Modified Pentium M		 Lg35 nm
Tox? nmGate DielectricSiO2
Vdd? V
2007 P1266 45 nm 9 Penryn,
Nehalem		 Lg25 nm
Tox? nmGate DielectricHigh-κ
Vdd? V
2009 P1268 32 nm 10 Westmere,
Sandy Bridge		 Lg30 nm
Tox? nmGate DielectricHigh-κ
Vdd? V
2011 P1270 22 nm 11 Ivy Bridge,
Haswell		 Lg26 nm
Tox? nmGate DielectricHigh-κ
Vdd? V
2014 P1272 14 nm 11 Broadwell,
Skylake,
Kaby Lake,
Coffee Lake		 Lg20 nm
Tox? nmGate DielectricHigh-κ
Vdd? V
2017 P1274 10 nm Cannonlake,
Icelake,
Tigerlake		 Lg18? nm
Tox? nmGate DielectricHigh-κ
Vdd? V
2019 P1276 7 nm
2022 P1278 5 nm
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