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Difference between revisions of "amd/ryzen 5/3550h"
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|series=3000
 
|series=3000
 
|frequency=2,100 MHz
 
|frequency=2,100 MHz
−
|turbo frequency1=3,700 MHz
+
|turbo frequency=3,700 MHz
 
|bus type=PCIe 3.0
 
|bus type=PCIe 3.0
 
|clock multiplier=21
 
|clock multiplier=21
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|temp min=0° C
 
|temp min=0° C
 
|temp max=105 °C
 
|temp max=105 °C
−
|package name 1=amd,socket_fp5
+
|package name 1=amd,fp5
 +
}}
 +
'''Ryzen 5 3550H''' is a {{arch|64}} [[quad-core]] mid-range performance [[x86]] mobile microprocessor introduced by [[AMD]] in early [[2019]].
 +
 
 +
This processor is based on AMD's {{amd|Zen+|Zen+ microarchitecture|l=arch}} and is fabricated on a [[12 nm process]]. The 3550H operates at a base frequency of 2.1 GHz with a [[TDP]] of 35 W and a {{amd|precision boost|boost}} frequency of 3.7 GHz. This APU supports up to 32 GiB of dual-channel DDR4-2400 memory and incorporates {{amd|Radeon Vega 8}} Graphics operating at up to 1.2 GHz.
 +
 
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=Yes
 +
|avx=Yes
 +
|avx2=Yes
 +
|avx512f=No
 +
|avx512cd=No
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=No
 +
|avx512dq=No
 +
|avx512vl=No
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=Yes
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=No
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=No
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=No
 +
|ht=No
 +
|vpro=No
 +
|vtx=No
 +
|vtd=No
 +
|ept=No
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|intqat=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=Yes
 +
|amdv=Yes
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=Yes
 +
|sensemi=Yes
 +
|xfr=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 
}}
 
}}
−
'''Ryzen 5 3550H''' is a {{arch|64}} [[quad-core]] mid-range performance [[x86]] mobile microprocessor introduced by [[AMD]] in early [[2019]]. This processor is based on AMD's {{amd|Zen+|Zen+ microarchitecture|l=arch}} and is fabricated on a [[12 nm process]]. The 3550H operates at a base frequency of 2.1 GHz with a [[TDP]] of 35 W and a {{amd|Precision Boost|Boost}} frequency of 3.7 GHz. This APU supports up to 32 GiB of dual-channel DDR4-2400 memory and incorporates {{amd|Radeon Vega 8}} Graphics operating at up to 1.2 GHz.
 
  
 
== Cache ==
 
== Cache ==
Line 54: Line 153:
 
|l3 break=1x4 MiB
 
|l3 break=1x4 MiB
 
}}
 
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2400
 +
|ecc=Yes
 +
|max mem=32 GiB
 +
|controllers=2
 +
|channels=2
 +
|max bandwidth=38.4 GB/s
 +
|bandwidth schan=19.2 GB/s
 +
|bandwidth dchan=38.4 GB/s
 +
}}
 +
 +
== Expansions ==
 +
This processor has 12 PCIe lanes, 1x8 typically designated for a [[GPU]] and 4 additional lanes for storage (e.g., NVMe).
 +
{{expansions main
 +
|
 +
{{expansions entry
 +
|type=PCIe
 +
|pcie revision=3.0
 +
|pcie lanes=12
 +
|pcie config=1x8+1x4
 +
|pcie config 2=2x4+1x4
 +
}}
 +
}}
 +
 +
== Graphics ==
 +
{{integrated graphics
 +
| gpu                = Radeon Vega 8
 +
| device id          =
 +
| designer            = AMD
 +
| execution units    = 8
 +
| unified shaders    = 512
 +
| max displays        = 4
 +
| max memory          =
 +
| frequency          =
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| max frequency      = 1,200 MHz
 +
 +
| output crt          =
 +
| output sdvo        =
 +
| output dsi          =
 +
| output edp          =
 +
| output dp          = Yes
 +
| output hdmi        = Yes
 +
| output vga          =
 +
| output dvi          =
 +
 +
| directx ver        = 12
 +
| opengl ver        = 4.6
 +
| opencl ver        = 2.2
 +
| hdmi ver          =
 +
| dp ver            =
 +
| edp ver            =
 +
| max res hdmi      =
 +
| max res hdmi freq  =
 +
| max res dp        =
 +
| max res dp freq    =
 +
| max res edp        =
 +
| max res edp freq  =
 +
| max res vga        =
 +
| max res vga freq  =
 +
}}
 +
{{zen with vega hardware accelerated video table|col=1}}
 +
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== Die ==
 +
{{further|amd/microarchitectures/zen+#Die|l1=Zen+ § Die}}
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* [[14 nm process]]
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* 4,940,000,000 transistors
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* 209.78 mm² die size
 +
 +
 +
: [[File:raven ridge die.png|650px]]
 +
 +
 +
: [[File:raven ridge die (annotated).png|650px]]

Latest revision as of 10:01, 4 November 2025

Edit Values
Ryzen 5 3550H
General Info
DesignerAMD
ManufacturerGlobalFoundries
Model Number3550H
Part NumberYM3500C4T4MFG
MarketMobile
IntroductionJanuary 6, 2019 (announced)
January 6, 2019 (launched)
ShopAmazon
General Specs
FamilyRyzen 5
Series3000
Frequency2,100 MHz
Turbo Frequency3,700 MHz
Bus typePCIe 3.0
Clock multiplier21
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureZen+
Core NamePicasso
Process12 nm
Transistors4,940,000,000
TechnologyCMOS
Die209.78 mm²
Word Size64 bit
Cores4
Threads8
Max Memory64 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP35 W
OP Temperature0° C – 105 °C
Packaging
PackageBGA-1140
Package TypeOrganic Micro Ball Grid Array
Dimension35 mm × 25 mm
Pitch0.7 mm
Contacts1140

Ryzen 5 3550H is a 64-bit quad-core mid-range performance x86 mobile microprocessor introduced by AMD in early 2019.

This processor is based on AMD's Zen+ microarchitecture and is fabricated on a 12 nm process. The 3550H operates at a base frequency of 2.1 GHz with a TDP of 35 W and a boost frequency of 3.7 GHz. This APU supports up to 32 GiB of dual-channel DDR4-2400 memory and incorporates Radeon Vega 8 Graphics operating at up to 1.2 GHz.

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
SSE4aStreaming SIMD Extensions 4a
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
SHASHA Extensions
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
SMTSimultaneous Multithreading
AMD-ViAMD-Vi (I/O MMU virtualization)
AMD-VAMD Virtualization
SenseMISenseMI Technology

Cache[edit]

Main article: Zen+ § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$384 KiB
393,216 B
0.375 MiB
L1I$256 KiB
262,144 B
0.25 MiB
4x64 KiB4-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  4x512 KiB8-way set associativewrite-back
L3$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  1x4 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2400
Supports ECCYes
Max Mem32 GiB
Controllers2
Channels2
Max Bandwidth38.4 GB/s
35.763 GiB/s
36,621.094 MiB/s
38,400 MB/s
0.0349 TiB/s
0.0384 TB/s
Bandwidth
Single 19.2 GB/s
Double 38.4 GB/s

Expansions[edit]

This processor has 12 PCIe lanes, 1x8 typically designated for a GPU and 4 additional lanes for storage (e.g., NVMe).

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 12
Configuration: 1x8+1x4, 2x4+1x4


Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPURadeon Vega 8
DesignerAMD
Execution Units8Max Displays4
Unified Shaders512
Burst Frequency1,200 MHz
1.2 GHz
1,200,000 KHz
OutputDP, HDMI
Standards
DirectX12
OpenGL4.6
OpenCL2.2

Die[edit]

Further information: Zen+ § Die


raven ridge die.png


raven ridge die (annotated).png
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/ryzen_5/3550h&oldid=103916"
Facts about "Ryzen 5 3550H - AMD"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Ryzen 5 3550H - AMD#pcie +
base frequency2,100 MHz (2.1 GHz, 2,100,000 kHz) +
bus typePCIe 3.0 +
clock multiplier21 +
core count4 +
core namePicasso +
designerAMD +
die area209.78 mm² (0.325 in², 2.098 cm², 209,780,000 µm²) +
familyRyzen 5 +
first announcedJanuary 6, 2019 +
first launchedJanuary 6, 2019 +
full page nameamd/ryzen 5/3550h +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has amd amd-v technologytrue +
has amd amd-vi technologytrue +
has amd sensemi technologytrue +
has ecc memory supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
integrated gpuRadeon Vega 8 +
integrated gpu designerAMD +
integrated gpu execution units8 +
integrated gpu max frequency1,200 MHz (1.2 GHz, 1,200,000 KHz) +
isax86-64 +
isa familyx86 +
l1$ size384 KiB (393,216 B, 0.375 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description4-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
l3$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldateJanuary 6, 2019 +
manufacturerGlobalFoundries +
market segmentMobile +
max cpu count1 +
max memory65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
max memory bandwidth35.763 GiB/s (36,621.094 MiB/s, 38.4 GB/s, 38,400 MB/s, 0.0349 TiB/s, 0.0384 TB/s) +
max memory channels2 +
max operating temperature105 °C +
microarchitectureZen+ +
min operating temperature0° C +
model number3550H +
nameRyzen 5 3550H +
packageBGA-1140 +
part numberYM3500C4T4MFG +
process12 nm (0.012 μm, 1.2e-5 mm) +
series3000 +
smp max ways1 +
supported memory typeDDR4-2400 +
tdp35 W (35,000 mW, 0.0469 hp, 0.035 kW) +
technologyCMOS +
thread count8 +
transistor count4,940,000,000 +
turbo frequency3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +