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Difference between revisions of "arm holdings/microarchitectures/hayes"
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{{armh title|Hayes|arch}}
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{{armh title|Cortex-A520|arch}}
 
{{microarchitecture
 
{{microarchitecture
 
|atype=CPU
 
|atype=CPU
−
|name=Hayes
+
|name=Cortex-A520
 
|designer=ARM Holdings
 
|designer=ARM Holdings
 
|manufacturer=TSMC
 
|manufacturer=TSMC
−
|manufacturer 2=Samsung
+
|manufacturer 2=
−
|manufacturer 3=GlobalFoundries
+
|introduction=Q4 2023
−
|manufacturer 4=SMIC
+
|process=4 nm
−
|introduction=2023
+
|process 2=
 +
|process 3=
 +
|cores=4
 +
|cores 2=
 +
|type=In-order
 +
|oooe=No
 +
|speculative=Yes
 +
|renaming=No
 +
|decode=3-way
 +
|isa=ARMv9.2-A
 +
|feature=Hardware virtualization
 +
|extension=FPU
 +
|extension 2=NEON
 +
|extension 3=SVE
 +
|extension 4=SVE2
 +
|extension 5=TrustZone
 +
|l1i=32-64 KiB
 +
|l1i per=core
 +
|l1i desc=4-way set associative
 +
|l1d=32-64 KiB
 +
|l1d per=core
 +
|l1d desc=4-way set associative
 +
|l2=0-512 KiB
 +
|l2 per=cluster
 +
|l2 desc=4-way set associative
 +
|l3=256 KiB-32 MiB
 +
|l3 desc=(optional)
 
|predecessor=Cortex-A510
 
|predecessor=Cortex-A510
 
|predecessor link=arm_holdings/microarchitectures/cortex-a510
 
|predecessor link=arm_holdings/microarchitectures/cortex-a510
 +
|successor=Cortex-A530
 +
|successor link=arm_holdings/microarchitectures/cortex-a530
 +
|successor 2=Cortex-A520AE
 +
|successor 2 link=arm_holdings/microarchitectures/cortex-a520ae
 
}}
 
}}
−
'''Hayes''' is is a planned ultra-high efficiency [[microarchitecture]] being designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A510|l=arch}}. Hayes is scheduled for introduction around the 2023 timeframe.
+
'''Cortex-A520''' (codename '''Hayes''') is a planned ultra-high efficiency {{armh|Cortex}} [[microarchitecture]] being designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A510|l=arch}}. Cortex-A520 is scheduled for introduction around the 2023 timeframe.
 +
 
 +
=== Process Technology ===
 +
The Cortex-A520 was primarily designed to take advantage of [[TSMC]]'s [[N4P|4 nm]] (TSMC N4P).
 +
<!--[[N7|7 nm]], [[N6|6 nm]], [[N5|5 nm]] as well as Samsung's [[7LPP|7 nm]] and [[5LPP|5 nm]]-->
 +
 
 +
=== Key changes from {{\\|Cortex-A510}} ===
 +
* Update to ARMv9.2-A <ref>{{cite web |title=Cortex-A520 |url=https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a520 |access-date=2023-06-05 |website=Arm {{!}} The Architecture for the Digital World }}</ref>
 +
* Support only 64-bit applications
 +
* Up to 512 KiB of private L2 cache (from 256 KiB)
 +
* 8% peak performance improvement over the Cortex-A510 <ref>{{cite web |title=Arm Unveils 2023 Mobile CPU Core Designs: Cortex-X4, A720, and A520 - the ARMv9.2 Family |url=https://www.anandtech.com/show/18871/arm-unveils-armv92-mobile-architecture-cortex-x4-a720-and-a520-64bit-exclusive |access-date=2023-06-05 |website=www.anandtech.com }}</ref>
 +
* Add QARMA3 Pointer Authentication (PAC) algorithm support
 +
 
 +
== Architecture comparison ==
 +
{| class="wikitable" style="text-align: center;
 +
|-
 +
!uArch
 +
!{{armh|Cortex-A53|l=arch}}
 +
!{{armh|Cortex-A55|l=arch}}
 +
!{{armh|Cortex-A510|l=arch}}
 +
!{{armh|Cortex-A520|l=arch}}
 +
!{{armh|Cortex-A530|l=arch}}
 +
|-
 +
!Codename
 +
|''Apollo''
 +
|''Ananke''
 +
|''Klein''
 +
|''{{armh|Hayes|l=arch}}''
 +
|''Nevis''
 +
|-
 +
!Peak clock speed
 +
|2.3&nbsp;GHz
 +
|2.1&nbsp;GHz
 +
|2.0&nbsp;GHz
 +
|2.0&nbsp;GHz
 +
|
 +
|-
 +
!Architecture
 +
|ARMv8.0-A
 +
|ARMv8.2-A
 +
|ARMv9.0-A
 +
|ARMv9.2-A
 +
|
 +
|-
 +
!'''AArch'''
 +
| colspan="3" |32-bit and 64-bit
 +
| 64-bit
 +
|
 +
|-
 +
!'''L1-I + L1-D'''
 +
|8/64 + 8/64 KiB
 +
|16/64 + 16/64 KiB
 +
| colspan="2" |32/64 + 32/64 KiB
 +
|
 +
|-
 +
!L2
 +
| colspan="2" |0–256 KiB
 +
| colspan="2" |0–512 KiB
 +
|
 +
|-
 +
!L3
 +
|?
 +
|0–4 MiB
 +
|0–16 MiB
 +
|0–32 MiB
 +
|
 +
|-
 +
!Decode Width
 +
| colspan="2" |2
 +
|3
 +
|3 (2 ALU)
 +
|
 +
|-
 +
!Dispatch
 +
| colspan="2" |8
 +
|
 +
|
 +
|
 +
|-
 +
|}
 +
 
 +
== Processors ==
 +
* [[Snapdragon 6]] Gen 4 (SM6650) • 4nm (TSMC N4P)
 +
:1× @2.3GHz Kryo Prime (Cortex-A720) +
 +
:3× @2.2GHz Kryo Gold (Cortex-A720) +
 +
:4× @1.8GHz Kryo Silver (Cortex-A520)
 +
* [[Snapdragon 7]]+ Gen 3 (SM7675-AB) • 4nm
 +
:1× 2.8 GHz Kryo Prime (Cortex-X4) +
 +
:4× 2.6 GHz Kryo Gold (Cortex-A720) +
 +
:3× 1.9 GHz Kryo Silver (Cortex-A520)
 +
* [[Snapdragon 7]]s Gen 3 (SM7635) • 4nm
 +
:1× @2.5GHz Kryo Prime (Cortex-A720) +
 +
:3× @2.4GHz Kryo Gold (Cortex-A720) +
 +
:4× @1.8GHz Kryo Silver (Cortex-A520)
 +
* [[Snapdragon 8]] Gen 3 (SM8650-AB) • 4 nm (TSMC N4P)
 +
:1× @3.3GHz Kryo Prime (Cortex-X4) +
 +
:3× @3.15GHz Kryo Gold (Cortex-A720) +
 +
:2× @2.96GHz Kryo Gold (Cortex-A720) +
 +
:2× @2.27GHz Kryo Silver (Cortex-A520)
 +
* [[Snapdragon 8]] Gen 3 (SM8650-AA)
 +
:1× @3.05GHz Kryo Prime (Cortex-X4) +
 +
:5× @2.96GHz Kryo Gold (Cortex-A720) +
 +
:2× @2.04GHz Kryo Silver (Cortex-A520) Q4 2024
 +
* [[Snapdragon 8]] Gen 3 for Galaxy (SM8650-AC)
 +
:1× @3.4GHz Kryo Prime (Cortex-X4) +
 +
:3× @3.15GHz Kryo Gold (Cortex-A720) +
 +
:2× @2.96GHz Kryo Gold (Cortex-A720) +
 +
:2× @2.27GHz Kryo Silver (Cortex-A520)
 +
* [[Snapdragon 8]]s Gen 3 (SM8635)
 +
:1× @3.0GHz Kryo Prime (Cortex-X4) +
 +
:4× @2.8GHz Kryo Gold (Cortex-A720) +
 +
:3× @2.0GHz Kryo Silver (Cortex-A520)
 +
 
 +
== See also ==
 +
* [[ARM]] • {{armh|Cortex}}
 +
 
 +
* {{qualcomm|Scorpion}} • {{qualcomm|Scorpion|l=arch}}
 +
* {{qualcomm|Krait}} • {{qualcomm|Krait|l=arch}}
 +
* {{qualcomm|Kryo}} • {{qualcomm|Kryo|l=arch}}
 +
* {{qualcomm|Oryon}} • {{qualcomm|Oryon|l=arch}}
 +
 
 +
* {{qualcomm|Hexagon|l=arch}}
 +
* {{qualcomm|Adreno|l=arch}}
 +
* {{qualcomm|Venus|l=arch}}
 +
 
 +
=== Reference ===

Latest revision as of 19:20, 21 February 2025

Edit Values
Cortex-A520 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionQ4 2023
Process4 nm
Core Configs4
Pipeline
TypeIn-order
OoOENo
SpeculativeYes
Reg RenamingNo
Decode3-way
Instructions
ISAARMv9.2-A
ExtensionsFPU, NEON, SVE, SVE2, TrustZone
Cache
L1I Cache32-64 KiB/core
4-way set associative
L1D Cache32-64 KiB/core
4-way set associative
L2 Cache0-512 KiB/cluster
4-way set associative
L3 Cache256 KiB-32 MiB
(optional)
Succession

Cortex-A520 (codename Hayes) is a planned ultra-high efficiency Cortex microarchitecture being designed by ARM Holdings as a successor to the Cortex-A510. Cortex-A520 is scheduled for introduction around the 2023 timeframe.

Process Technology[edit]

The Cortex-A520 was primarily designed to take advantage of TSMC's 4 nm (TSMC N4P).

Key changes from Cortex-A510[edit]

  • Update to ARMv9.2-A [1]
  • Support only 64-bit applications
  • Up to 512 KiB of private L2 cache (from 256 KiB)
  • 8% peak performance improvement over the Cortex-A510 [2]
  • Add QARMA3 Pointer Authentication (PAC) algorithm support

Architecture comparison[edit]

uArch Cortex-A53 Cortex-A55 Cortex-A510 Cortex-A520 Cortex-A530
Codename Apollo Ananke Klein Hayes Nevis
Peak clock speed 2.3 GHz 2.1 GHz 2.0 GHz 2.0 GHz
Architecture ARMv8.0-A ARMv8.2-A ARMv9.0-A ARMv9.2-A
AArch 32-bit and 64-bit 64-bit
L1-I + L1-D 8/64 + 8/64 KiB 16/64 + 16/64 KiB 32/64 + 32/64 KiB
L2 0–256 KiB 0–512 KiB
L3 ? 0–4 MiB 0–16 MiB 0–32 MiB
Decode Width 2 3 3 (2 ALU)
Dispatch 8

Processors[edit]

1× @2.3GHz Kryo Prime (Cortex-A720) +
3× @2.2GHz Kryo Gold (Cortex-A720) +
4× @1.8GHz Kryo Silver (Cortex-A520)
1× 2.8 GHz Kryo Prime (Cortex-X4) +
4× 2.6 GHz Kryo Gold (Cortex-A720) +
3× 1.9 GHz Kryo Silver (Cortex-A520)
1× @2.5GHz Kryo Prime (Cortex-A720) +
3× @2.4GHz Kryo Gold (Cortex-A720) +
4× @1.8GHz Kryo Silver (Cortex-A520)
1× @3.3GHz Kryo Prime (Cortex-X4) +
3× @3.15GHz Kryo Gold (Cortex-A720) +
2× @2.96GHz Kryo Gold (Cortex-A720) +
2× @2.27GHz Kryo Silver (Cortex-A520)
1× @3.05GHz Kryo Prime (Cortex-X4) +
5× @2.96GHz Kryo Gold (Cortex-A720) +
2× @2.04GHz Kryo Silver (Cortex-A520) Q4 2024
1× @3.4GHz Kryo Prime (Cortex-X4) +
3× @3.15GHz Kryo Gold (Cortex-A720) +
2× @2.96GHz Kryo Gold (Cortex-A720) +
2× @2.27GHz Kryo Silver (Cortex-A520)
1× @3.0GHz Kryo Prime (Cortex-X4) +
4× @2.8GHz Kryo Gold (Cortex-A720) +
3× @2.0GHz Kryo Silver (Cortex-A520)

See also[edit]

Reference[edit]

  1. ↑ Template:cite web
  2. ↑ Template:cite web
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/hayes&oldid=102824"
Facts about "Cortex-A520 - Microarchitectures - ARM"
RDF feed
codenameCortex-A520 +
core count4 +
designerARM Holdings +
first launchedApril 2023 +
full page namearm holdings/microarchitectures/hayes +
instance ofmicroarchitecture +
instruction set architectureARMv9.2-A +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A520 +
process4 nm (0.004 μm, 4.0e-6 mm) +