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Difference between revisions of "amd/microarchitectures/zen 5"
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|designer=AMD
 
|designer=AMD
 
|manufacturer=TSMC
 
|manufacturer=TSMC
−
|process=N4X
+
|introduction=2024
 +
|process=4 nm
 +
|process 2=N4X
 
|cores=256
 
|cores=256
 
|cores 2=224
 
|cores 2=224
Line 20: Line 22:
 
|cores 13=36
 
|cores 13=36
 
|cores 14=24
 
|cores 14=24
−
|cores 18=18
+
|cores 15=18
 
|cores 16=16
 
|cores 16=16
−
|cores 8=8
+
|cores 17=8
−
|cores 6=6
+
|cores 18=6
 
|processing elements=512
 
|processing elements=512
 
|processing elements 2=448
 
|processing elements 2=448
Line 44: Line 46:
 
|speculative=Yes
 
|speculative=Yes
 
|renaming=Yes
 
|renaming=Yes
−
|isa=x86-64
+
|isa=AMD64
−
|isa 2=AVX512, AMX (Advanced Matrix Extensions)
+
|isa 2=x86-64
 +
|extension=AMX <!-- (Advanced Matrix Extensions) -->
 +
|extension 2=AVX
 +
|extension 3=AVX2
 +
|extension 4=AVX-512
 
|feature=SHA
 
|feature=SHA
−
|feature 2=XFR 3 or 4 ( Extended frequency range)
+
|feature 2=XFR 3 or 4 <!-- (Extended frequency range) -->
−
|core name=Turin (EPYC server multiprocessor)
+
|core name={{amd|Turin|l=arch}} <!-- (EPYC server multiprocessor) -->
−
|core name 2=Da Vinci (Threadripper Workstation)
+
|core name 2={{amd|Da Vinci|l=arch}} <!-- (Threadripper Workstation) -->
−
|core name 3=Granite Ridge (Gaming Desktop CPU)
+
|core name 3={{amd|Granite Ridge|l=arch}} <!-- (Gaming Desktop CPU) -->
−
|core name 4=Strix Point (Gaming APU with RDNA3 or RDNA4)
+
|core name 4={{amd|Strix Point|l=arch}} <!-- (Gaming APU with RDNA3 or RDNA4) -->
 +
|succession=Yes
 
|predecessor=Zen 4
 
|predecessor=Zen 4
 
|predecessor link=amd/microarchitectures/zen 4
 
|predecessor link=amd/microarchitectures/zen 4
−
|successor=Zen 6 or maybe a completely new microarchitecture
+
|successor=Zen 6 <!-- or maybe a completely new microarchitecture -->
−
|succession=Yes
+
|successor link=amd/microarchitectures/zen 6
 
}}
 
}}
−
'''Zen 5''' is a [[microarchitecture]]Already released and sold being  by [[AMD]] as a successor to {{\\|Zen 4}}.
+
 
 +
'''Zen 5''' is a [[microarchitecture]] Already released and sold being  by [[AMD]] as a successor to {{\\|Zen 4}}
  
 
== History ==
 
== History ==
−
Zen 5 was first mentioned by lead architect Michael Clark during a discussion on April 9th, 2018<ref>[https://www.youtube.com/watch?v=iQ_4C2TKHQ0 Ryzen™ Processors: One Year Later]</ref>.
+
Zen 5 was first mentioned by lead architect Michael Clark during a discussion on April 9th, 2018 <ref>[https://www.youtube.com/watch?v=iQ_4C2TKHQ0 Ryzen Processors: One Year Later]</ref>
  
 
== Codenames ==
 
== Codenames ==
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{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
−
! Core !! C/T !! Target
+
! Model !! Core !! C/T !! Target
 
|-
 
|-
−
| {{amd|Turin|l=core}} || Up to ?/? || High-end server [[multiprocessors]]
+
| {{amd|EPYC 9005}} || {{amd|Turin|l=core}} || Up to ?/? || High-end EPYC server [[multiprocessors]])
 
|-
 
|-
−
| {{amd|Da Vinci|l=core}} || Up to ?/? || Workstation & enthusiasts market processors
+
| - || {{amd|Da Vinci|l=core}} || Up to ?/? || Threadripper Workstation & enthusiasts market processors
 
|-
 
|-
−
| {{amd|Granite Ridge|l=core}} || Up to ?/? || Mainstream to high-end desktops & enthusiasts market processors
+
| {{amd|Ryzen 9000}} || {{amd|Granite Ridge|l=core}} || Up to ?/? || Mainstream to high-end desktops & enthusiasts market processors<br>(Gaming Desktop CPU)
 
|-
 
|-
−
| {{amd|Strix Point|l=core}} || Up to ?/? || Mainstream desktop & mobile processors with GPU
+
| {{amd|Ryzen AI 300}} || {{amd|Strix Point|l=core}} || Up to ?/? || Mainstream desktop & mobile processors with GPU<br>(Gaming APU with RDNA3 or RDNA4)
 
|}
 
|}
 +
 +
The Zen 5 microarchitecture powers Ryzen 9000 series desktop processors (codenamed "Granite Ridge"), Epyc 9005 server
 +
:processors (codenamed "Turin"), and Ryzen AI 300 thin and light mobile processors (codenamed "Strix Point").
  
 
'''Architectural Codenames:'''
 
'''Architectural Codenames:'''
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| CCD || Eldora
 
| CCD || Eldora
 
|}
 
|}
 +
<!-- Aspen, Vail, Breckenridge, Loveland, Durango, Monarch - Colorado -->
 +
 +
{| class="wikitable" style="text-align: center;"
 +
! colspan="2" | Core
 +
! {{amd|Zen|l=arch}}
 +
! {{amd|Zen+|l=arch}}
 +
! {{amd|Zen 2|l=arch}}
 +
! {{amd|Zen 3|l=arch}}
 +
! {{amd|Zen 3+|l=arch}}
 +
! {{amd|Zen 4|l=arch}}
 +
! {{amd|Zen 4c|l=arch}}
 +
! {{amd|Zen 5|l=arch}}
 +
! {{amd|Zen 5c|l=arch}}
 +
! {{amd|Zen 6|l=arch}}
 +
! {{amd|Zen 6c|l=arch}}
 +
|-
 +
! style="text-align: left;" rowspan="2" | Codename
 +
! style="text-align: left;" | Core
 +
|
 +
|
 +
| ''Valhalla''
 +
| ''Cerberus''
 +
|
 +
| ''Persephone''
 +
| ''Dionysus''
 +
| ''Nirvana''
 +
| ''Prometheus''
 +
| ''Morpheus''
 +
| ''Monarch''
 +
|-
 +
! style="text-align: left;" | CCD
 +
|
 +
|
 +
| ''Aspen <br>Highlands''
 +
| ''Breckenridge''
 +
|
 +
| ''Durango''
 +
| ''Vindhya''
 +
| ''Eldora''
 +
|
 +
|
 +
|
 +
|-
 +
! style="text-align: left;" rowspan="2" | Cores <br>(threads)
 +
! style="text-align: left;" | CCD
 +
|
 +
|
 +
|
 +
| 8 (16)
 +
|
 +
| 8 (16)
 +
| 16 (32)
 +
|
 +
|
 +
|
 +
|
 +
|-
 +
! style="text-align: left;" | CCX
 +
|
 +
|
 +
|
 +
| 8 (16)
 +
|
 +
| 8 (16)
 +
| 8 (16)
 +
|
 +
|
 +
|
 +
|
 +
|-
 +
! style="text-align: left;" rowspan="2" | L3 cache
 +
! style="text-align: left;" | CCD
 +
|
 +
|
 +
|
 +
| 32 MB
 +
|
 +
| 32 MB
 +
| 32 MB
 +
| 32 MB
 +
|
 +
|
 +
|
 +
|-
 +
! style="text-align: left;" | CCX
 +
|
 +
|
 +
|
 +
| 32 MB
 +
|
 +
| 32 MB
 +
| 16 MB
 +
| 32 MB
 +
|
 +
|
 +
|
 +
|-
 +
! style="text-align: left;" rowspan="2" | Die size
 +
! style="text-align: left;" | CCD area
 +
| 44 mm<sup>2</sup>
 +
|
 +
|
 +
|
 +
|
 +
| 66.3 mm<sup>2</sup>
 +
| 72.7 mm<sup>2</sup>
 +
| 70.6 mm<sup>2</sup>
 +
|
 +
|
 +
|
 +
|-
 +
! style="text-align: left;" | Core area
 +
| 7 mm<sup>2</sup><br>(14 nm)
 +
| (14 nm)
 +
| (7 nm)
 +
| (7 nm)
 +
| (7 nm)
 +
| 3.84 mm<sup>2</sup><br>(5 nm)
 +
| 2.48 mm<sup>2</sup><br>(5 nm)
 +
| (4 nm)
 +
| (3 nm)
 +
| (2 nm)
 +
| (2 nm)
 +
|-
 +
|}
 +
 +
===Models===
 +
{{collist
 +
| count = 4
 +
|
 +
* {{amd|Zen|l=arch}}
 +
* {{amd|Zen+|l=arch}}
 +
* {{amd|Zen 2|l=arch}} (Valhalla) <!-- (CCD: Aspen Highlands) -->
 +
* {{amd|Zen 3|l=arch}} (Cerberus) <!-- (CCD: Breckenridge) -->
 +
* {{amd|Zen 3+|l=arch}}
 +
* {{amd|Zen 4|l=arch}} (Persephone) <!-- (CCD: Durango) -->
 +
* {{amd|Zen 4c|l=arch}} (Dionysus) <!-- (CCD: Vindhya) -->
 +
* {{amd|Zen 5|l=arch}} (Nirvana) <!-- (CCD: Eldora) -->
 +
* {{amd|Zen 5c|l=arch}} (Prometheus)
 +
* {{amd|Zen 6|l=arch}} (Morpheus)
 +
* {{amd|Zen 6c|l=arch}} (Monarch)
 +
* {{amd|Zen 7|l=arch}}
 +
}}
  
 
== Process Technology ==
 
== Process Technology ==
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LITTLE design
 
LITTLE design
−
-Improved 16% IPC and clock speed
+
- Improved 16% IPC and clock speed
 
- possibly more L3 cache per chiplet
 
- possibly more L3 cache per chiplet
  

Latest revision as of 17:21, 12 February 2025

Edit Values
Zen 5 µarch
General Info
Arch TypeCPU
DesignerAMD
ManufacturerTSMC
Introduction2024
Process4 nm, N4X
Core Configs256, 224, 192, 144, 128, 96, 72, 64, 56, 48, 32, 28, 36, 24, 18, 16, 8, 6
PE Configs512, 448, 384, 288, 256, 192, 144, 128, 112, 96, 64, 56, 60, 40, 30, 20
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAAMD64, x86-64
ExtensionsAMX, AVX, AVX2, AVX-512
Cores
Core NamesTurin,
Da Vinci,
Granite Ridge,
Strix Point
Succession

Zen 5 is a microarchitecture Already released and sold being by AMD as a successor to Zen 4

History[edit]

Zen 5 was first mentioned by lead architect Michael Clark during a discussion on April 9th, 2018 [1]

Codenames[edit]

Product Codenames:

Model Core C/T Target
EPYC 9005 Turin Up to ?/? High-end EPYC server multiprocessors)
- Da Vinci Up to ?/? Threadripper Workstation & enthusiasts market processors
Ryzen 9000 Granite Ridge Up to ?/? Mainstream to high-end desktops & enthusiasts market processors
(Gaming Desktop CPU)
Ryzen AI 300 Strix Point Up to ?/? Mainstream desktop & mobile processors with GPU
(Gaming APU with RDNA3 or RDNA4)

The Zen 5 microarchitecture powers Ryzen 9000 series desktop processors (codenamed "Granite Ridge"), Epyc 9005 server

processors (codenamed "Turin"), and Ryzen AI 300 thin and light mobile processors (codenamed "Strix Point").

Architectural Codenames:

Arch Codename
Core Nirvana
CCD Eldora
Core Zen Zen+ Zen 2 Zen 3 Zen 3+ Zen 4 Zen 4c Zen 5 Zen 5c Zen 6 Zen 6c
Codename Core Valhalla Cerberus Persephone Dionysus Nirvana Prometheus Morpheus Monarch
CCD Aspen
Highlands 		Breckenridge Durango Vindhya Eldora
Cores
(threads) 		CCD 8 (16) 8 (16) 16 (32)
CCX 8 (16) 8 (16) 8 (16)
L3 cache CCD 32 MB 32 MB 32 MB 32 MB
CCX 32 MB 32 MB 16 MB 32 MB
Die size CCD area 44 mm2 66.3 mm2 72.7 mm2 70.6 mm2
Core area 7 mm2
(14 nm) 		(14 nm) (7 nm) (7 nm) (7 nm) 3.84 mm2
(5 nm) 		2.48 mm2
(5 nm) 		(4 nm) (3 nm) (2 nm) (2 nm)

Models[edit]

Process Technology[edit]

Zen 5 is to be produced on a 4nm process,Zen 5c is to be produced on a 3nm process.

Architecture[edit]

LITTLE design - Improved 16% IPC and clock speed - possibly more L3 cache per chiplet

Key changes from Zen 4[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Designers[edit]

  • David Suggs, chief architect

Bibliography[edit]

  1. ↑ Ryzen Processors: One Year Later

See Also[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/microarchitectures/zen_5&oldid=102774"
Facts about "Zen 5 - Microarchitectures - AMD"
RDF feed
codenameZen 5 +
core count256 +, 224 +, 192 +, 144 +, 128 +, 96 +, 72 +, 64 +, 56 +, 48 +, 32 +, 28 +, 36 +, 24 +, 18 +, 16 +, 8 + and 6 +
designerAMD +
first launched2024 +
full page nameamd/microarchitectures/zen 5 +
instance ofmicroarchitecture +
instruction set architectureAMD64 + and x86-64 +
manufacturerTSMC +
microarchitecture typeCPU +
nameZen 5 +
process4 nm (0.004 μm, 4.0e-6 mm) +
processing element count512 +, 448 +, 384 +, 288 +, 256 +, 192 +, 144 +, 128 +, 112 +, 96 +, 64 +, 56 +, 60 +, 40 +, 30 + and 20 +