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Difference between revisions of "phytium/feiteng/ft-2000+-64"
< phytium‎ | feiteng

 
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|first announced=2019
 
|first announced=2019
 
|first launched=2019
 
|first launched=2019
−
|family=FT-2000
+
|family=FeiTeng
−
|frequency=2,3000 MHz
+
|series=FT-2000+
 +
|frequency=2,300 MHz
 
|isa=ARMv8.0
 
|isa=ARMv8.0
 
|isa family=ARM
 
|isa family=ARM
 
|microarch=Mars II
 
|microarch=Mars II
 +
|microarch 2=Xiaomi
 
|core name=FTC-662
 
|core name=FTC-662
 
|process=16 nm
 
|process=16 nm
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|die area=370 mm²
 
|die area=370 mm²
 
|word size=64 bit
 
|word size=64 bit
 +
|core count=64
 +
|thread count=64
 +
|max cpus=1
 
|tdp=96 W
 
|tdp=96 W
 
|package name 1=phytium,fcbga_3576
 
|package name 1=phytium,fcbga_3576
 
|predecessor=FT-2000/64
 
|predecessor=FT-2000/64
−
|predecessor link=phytium/ft-2000/ft-2000-64
+
|predecessor link=phytium/feiteng/ft-2000-64
 
}}
 
}}
 
'''FT-2000+/64''' is a [[64 core]] [[ARM]] server SoC designed by [[Phytium]] and introduced in [[2019]]. Fabricated on [[TSMC]]'s [[16 nm process]], the chip operates at up 2.3 GHz with a TDP of 96 W. This chip is designed for server, communication, and infrastructure applications.
 
'''FT-2000+/64''' is a [[64 core]] [[ARM]] server SoC designed by [[Phytium]] and introduced in [[2019]]. Fabricated on [[TSMC]]'s [[16 nm process]], the chip operates at up 2.3 GHz with a TDP of 96 W. This chip is designed for server, communication, and infrastructure applications.
 +
 +
== Cache ==
 +
{{main|phytium/microarchitectures/mars_ii#Memory_Hierarchy|l1=Mars II § Cache}}
 +
{{cache size
 +
|l1 cache=4 MiB
 +
|l1i cache=2 MiB
 +
|l1i break=64x32 KiB
 +
|l1d cache=2 MiB
 +
|l1d break=64x32 KiB
 +
|l2 cache=32 MiB
 +
|l2 break=16x2 MiB
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-3200
 +
|ecc=Yes
 +
|controllers=8
 +
|channels=8
 +
|max bandwidth=143.1 GiB/s
 +
|bandwidth schan=17.88 GiB/s
 +
|bandwidth dchan=35.76 GiB/s
 +
|bandwidth qchan=71.53 GiB/s
 +
|bandwidth hchan=107.3 GiB/s
 +
|bandwidth ochan=143.1 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 33
 +
| pcie config        = 4x8+x1
 +
| pcie config 2      =
 +
| sata revision      =
 +
| sata ports        =
 +
| usb revision      =
 +
| usb revision 2    =
 +
| usb ports          =
 +
| usb rate          =
 +
| uart              =
 +
| uart ports        =
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| gp io              =
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}}
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== Die ==
 +
{{main|phytium/microarchitectures/mars_ii#Die|l1=Mars II § Die}}
 +
:[[File:mars ii die.png|400px]]
 +
 +
 +
:[[File:mars ii die (annotated).png|400px]]

Latest revision as of 03:41, 17 July 2023

Edit Values
FT-2000+/64
ft-2000+-64 (front).png
General Info
DesignerPhytium
ManufacturerTSMC
Model NumberFT-2000+/64
MarketServer
Introduction2019 (announced)
2019 (launched)
General Specs
FamilyFeiTeng
SeriesFT-2000+
Frequency2,300 MHz
Microarchitecture
ISAARMv8.0 (ARM)
MicroarchitectureMars II, Xiaomi
Core NameFTC-662
Process16 nm
Transistors6,000,000,000
TechnologyCMOS
Die370 mm²
Word Size64 bit
Cores64
Threads64
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP96 W
Packaging
PackageFCBGA-3576 (BGA)
Dimension61 mm × 61 mm
Contacts3576
ft-2000+-64 (back).png
Succession

FT-2000+/64 is a 64 core ARM server SoC designed by Phytium and introduced in 2019. Fabricated on TSMC's 16 nm process, the chip operates at up 2.3 GHz with a TDP of 96 W. This chip is designed for server, communication, and infrastructure applications.

Cache[edit]

Main article: Mars II § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$4 MiB
4,096 KiB
4,194,304 B
L1I$2 MiB
2,048 KiB
2,097,152 B
64x32 KiB  
L1D$2 MiB
2,048 KiB
2,097,152 B
64x32 KiB  
L2$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  16x2 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-3200
Supports ECCYes
Controllers8
Channels8
Max Bandwidth143.1 GiB/s
146,534.4 MiB/s
153.652 GB/s
153,652.455 MB/s
0.14 TiB/s
0.154 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s
Quad 71.53 GiB/s
Hexa 107.3 GiB/s
Octa 143.1 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes33
Configs4x8+x1


Die[edit]

Main article: Mars II § Die
mars ii die.png


mars ii die (annotated).png
Retrieved from "https://en.wikichip.org/w/index.php?title=phytium/feiteng/ft-2000%2B-64&oldid=101849"
Facts about "FT-2000+/64 - Phytium"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
FT-2000+/64 - Phytium#io +
back imageFile:ft-2000+-64 (back).png +
base frequency2,300 MHz (2.3 GHz, 2,300,000 kHz) +
core count64 +
core nameFTC-662 +
designerPhytium +
die area370 mm² (0.574 in², 3.7 cm², 370,000,000 µm²) +
familyFeiTeng +
first announced2019 +
first launched2019 +
full page namephytium/feiteng/ft-2000+-64 +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaARMv8.0 +
isa familyARM +
l1$ size4,096 KiB (4,194,304 B, 4 MiB) +
l1d$ size2,048 KiB (2,097,152 B, 2 MiB) +
l1i$ size2,048 KiB (2,097,152 B, 2 MiB) +
l2$ size32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldate2019 +
main imageFile:ft-2000+-64 (front).png +
manufacturerTSMC +
market segmentServer +
max cpu count1 +
max memory bandwidth143.1 GiB/s (146,534.4 MiB/s, 153.652 GB/s, 153,652.455 MB/s, 0.14 TiB/s, 0.154 TB/s) +
max memory channels8 +
max pcie lanes33 +
microarchitectureMars II + and Xiaomi +
model numberFT-2000+/64 +
nameFT-2000+/64 +
packageFCBGA-3576 +
process16 nm (0.016 μm, 1.6e-5 mm) +
seriesFT-2000+ +
smp max ways1 +
supported memory typeDDR4-3200 +
tdp96 W (96,000 mW, 0.129 hp, 0.096 kW) +
technologyCMOS +
thread count64 +
transistor count6,000,000,000 +
word size64 bit (8 octets, 16 nibbles) +