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Difference between revisions of "amd/microarchitectures/zen 5"
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{{amd title|Zen 5|arch}}
 
{{amd title|Zen 5|arch}}
 
{{microarchitecture
 
{{microarchitecture
−
|atype=CPUjdjfjebcbs c e
+
|atype=CPU
 
|name=Zen 5
 
|name=Zen 5
 
|designer=AMD
 
|designer=AMD
 
|manufacturer=TSMC or Samsung
 
|manufacturer=TSMC or Samsung
−
|process=5 nm
+
|process=3 nm
 +
|cores=256
 +
|cores 2=224
 +
|cores 3=192
 +
|cores 4=144
 +
|cores 5=128
 +
|cores 6=96
 +
|cores 7=72
 +
|cores 8=64
 +
|cores 9=56
 +
|cores 10=48
 +
|cores 11=32
 +
|cores 12=28
 +
|cores 13=36
 +
|cores 14=24
 +
|cores 15=18
 +
|cores 16=12
 +
|processing elements=512
 +
|processing elements 2=448
 +
|processing elements 3=384
 +
|processing elements 4=288
 +
|processing elements 5=256
 +
|processing elements 6=192
 +
|processing elements 7=144
 +
|processing elements 8=128
 +
|processing elements 9=112
 +
|processing elements 10=96
 +
|processing elements 11=64
 +
|processing elements 12=56
 +
|processing elements 13=60
 +
|processing elements 14=40
 +
|processing elements 15=30
 +
|processing elements 16=20
 +
|type=Superscalar
 +
|oooe=Yes
 +
|speculative=Yes
 +
|renaming=Yes
 +
|isa=x86-64
 +
|isa 2=AVX512, AMX (Advanced Matrix Extensions)
 +
|feature=SHA
 +
|feature 2=XFR 3 or 4 ( Extended frequency range)
 +
|core name=Turin (EPYC server multiprocessor)
 +
|core name 2=Da Vinci (Threadripper Workstation)
 +
|core name 3=Granite Ridge (Gaming Desktop CPU)
 +
|core name 4=Strix Point (Gaming APU with RDNA3 or RDNA4)
 
|predecessor=Zen 4
 
|predecessor=Zen 4
 
|predecessor link=amd/microarchitectures/zen 4
 
|predecessor link=amd/microarchitectures/zen 4
 +
|successor=Zen 6 or maybe a completely new microarchitecture
 
|succession=Yes
 
|succession=Yes
 
}}
 
}}
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== History ==
 
== History ==
 
Zen 5 was first mentioned by lead architect Michael Clark during a discussion on April 9th, 2018<ref>[https://www.youtube.com/watch?v=iQ_4C2TKHQ0 Ryzen™ Processors: One Year Later]</ref>.
 
Zen 5 was first mentioned by lead architect Michael Clark during a discussion on April 9th, 2018<ref>[https://www.youtube.com/watch?v=iQ_4C2TKHQ0 Ryzen™ Processors: One Year Later]</ref>.
 +
 +
== Codenames ==
 +
'''Product Codenames:'''
 +
{| class="wikitable"
 +
|-
 +
! Core !! C/T !! Target
 +
|-
 +
| {{amd|Turin|l=core}} || Up to ?/? || High-end server [[multiprocessors]]
 +
|-
 +
| {{amd|Da Vinci|l=core}} || Up to ?/? || Workstation & enthusiasts market processors
 +
|-
 +
| {{amd|Granite Ridge|l=core}} || Up to ?/? || Mainstream to high-end desktops & enthusiasts market processors
 +
|-
 +
| {{amd|Strix Point|l=core}} || Up to ?/? || Mainstream desktop & mobile processors with GPU
 +
|}
 +
 +
'''Architectural Codenames:'''
 +
{| class="wikitable"
 +
|-
 +
! Arch !! Codename
 +
|-
 +
| Core || Nirvana
 +
|-
 +
| CCD || Eldora
 +
|}
  
 
== Process Technology ==
 
== Process Technology ==
−
Zen 5 is speculated to be produced on a [[5nm process]].
+
Zen 5 is speculated to be produced on a [[3nm process]].
  
−
== Codenames ==
+
== Architecture ==
−
{{empty section}}
+
Little is currently known about the architectural improvements that are being done to Zen 5.
  
−
== Architecture ==
+
-big.LITTLE design
−
Nothing is currently known about the architectural improvements that are being done to Zen 5.
+
-More IPC and clock speed
 +
- possibly more L3 cache per chiplet
  
 
=== Key changes from {{\\|Zen 4}} ===
 
=== Key changes from {{\\|Zen 4}} ===

Revision as of 21:33, 9 October 2022

Edit Values
Zen 5 µarch
General Info
Arch TypeCPU
DesignerAMD
ManufacturerTSMC or Samsung
Process3 nm
Core Configs256, 224, 192, 144, 128, 96, 72, 64, 56, 48, 32, 28, 36, 24, 18, 12
PE Configs512, 448, 384, 288, 256, 192, 144, 128, 112, 96, 64, 56, 60, 40, 30, 20
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAx86-64, AVX512, AMX (Advanced Matrix Extensions)
Cores
Core NamesTurin (EPYC server multiprocessor),
Da Vinci (Threadripper Workstation),
Granite Ridge (Gaming Desktop CPU),
Strix Point (Gaming APU with RDNA3 or RDNA4)
Succession

Zen 5 is a planned microarchitecture being developed by AMD as a successor to Zen 4.

History

Zen 5 was first mentioned by lead architect Michael Clark during a discussion on April 9th, 2018[1].

Codenames

Product Codenames:

Core C/T Target
Turin Up to ?/? High-end server multiprocessors
Da Vinci Up to ?/? Workstation & enthusiasts market processors
Granite Ridge Up to ?/? Mainstream to high-end desktops & enthusiasts market processors
Strix Point Up to ?/? Mainstream desktop & mobile processors with GPU

Architectural Codenames:

Arch Codename
Core Nirvana
CCD Eldora

Process Technology

Zen 5 is speculated to be produced on a 3nm process.

Architecture

Little is currently known about the architectural improvements that are being done to Zen 5.

-big.LITTLE design -More IPC and clock speed - possibly more L3 cache per chiplet

Key changes from Zen 4

New text document.svg This section is empty; you can help add the missing info by editing this page.

Designers

  • David Suggs, chief architect

Bibliography

  1. ↑ Ryzen™ Processors: One Year Later

See Also

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/microarchitectures/zen_5&oldid=100840"
Facts about "Zen 5 - Microarchitectures - AMD"
RDF feed
codenameZen 5 +
core count256 +, 224 +, 192 +, 144 +, 128 +, 96 +, 72 +, 64 +, 56 +, 48 +, 32 +, 28 +, 36 +, 24 +, 18 + and 12 +
designerAMD +
full page nameamd/microarchitectures/zen 5 +
instance ofmicroarchitecture +
instruction set architecturex86-64 + and AVX512, AMX (Advanced Matrix Extensions) +
manufacturerTSMC or Samsung +
microarchitecture typeCPU +
nameZen 5 +
process3 nm (0.003 μm, 3.0e-6 mm) +
processing element count512 +, 448 +, 384 +, 288 +, 256 +, 192 +, 144 +, 128 +, 112 +, 96 +, 64 +, 56 +, 60 +, 40 +, 30 + and 20 +