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Difference between revisions of "intel/microarchitectures/comet lake"
< intel‎ | microarchitectures

(fix layout of previous edit)
 
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Line 6: Line 6:
 
|manufacturer=Intel
 
|manufacturer=Intel
 
|process=14 nm
 
|process=14 nm
−
|cores=2
+
|cores=4
−
|cores 2=4
 
−
|cores 3=6
 
−
|cores 4=8
 
 
|type=Superscalar
 
|type=Superscalar
 
|type 2=Superpipeline
 
|type 2=Superpipeline
Line 65: Line 62:
 
|l4 desc=on Iris Pro GPUs only
 
|l4 desc=on Iris Pro GPUs only
 
|core name=Comet Lake U
 
|core name=Comet Lake U
−
|predecessor=Whiskey Lake
+
|core name 2=Comet Lake S
−
|predecessor link=intel/microarchitectures/whiskey lake
+
|predecessor=Coffee Lake
−
|successor=Ice Lake
+
|predecessor link=intel/microarchitectures/coffee lake
−
|successor link=intel/microarchitectures/ice lake (client)
+
|predecessor 2=Whiskey Lake
−
|contemporary=Coffee Lake
+
|predecessor 2 link=intel/microarchitectures/whiskey lake
−
|contemporary link=intel/microarchitectures/coffee lake
+
|successor=Rocket Lake
−
|contemporary 2=Amber Lake
+
|successor link=intel/microarchitectures/rocket lake
−
|contemporary 2 link=intel/microarchitectures/amber lake
 
 
}}
 
}}
−
'''Comet Lake''' ('''CML''') is a planned [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Whiskey Lake}} for ultra-low power mobile devices, launched concurrently with {{\\|Coffee Lake}} and {{\\|Amber Lake}}.
+
'''Comet Lake''' ('''CML''') is [[Intel]]'s successor to {{\\|Coffee Lake}}, an enhanced [[14 nm process]] [[microarchitecture]] for mainstream desktops and mobile devices.
−
 
 
−
 
 
−
{{future information}}
 
  
 +
For desktop and mobile, Comet Lake is branded as 10th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}, {{intel|Core i7}}, and {{intel|Core i9}} processors.
  
 
== Codenames ==
 
== Codenames ==
Line 84: Line 78:
 
|-
 
|-
 
! Core !! Abbrev !! Description !! Graphics !! Target
 
! Core !! Abbrev !! Description !! Graphics !! Target
 +
|-
 +
| {{intel|Comet Lake S|l=core}} || CML-S || Mainstream performance || GT2 || Desktop performance to value, AiOs, and minis
 
|-
 
|-
 
| {{intel|Comet Lake U|l=core}} || CML-U || Ultra-low power|| GT2 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
 
| {{intel|Comet Lake U|l=core}} || CML-U || Ultra-low power|| GT2 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
Line 89: Line 85:
  
 
== Brands ==
 
== Brands ==
−
Intel released Coffee Lake under 3 main brand families:
+
Intel has released Comet Lake under 4 main brand families:
  
 
{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;"
 
{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;"
Line 97: Line 93:
 
! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]
 
! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]
 
|-
 
|-
−
| [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || {{intel|Core i3}} || Low-end Performance || ? ||  
+
| [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || {{intel|Core i3}} || Low-end Performance || [[quad-core|Quad]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
 +
|-
 +
| [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || Mid-range Performance || [[hexa-core|Hexa]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
 
|-
 
|-
−
| [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || Mid-range Performance || ? ||  
+
| [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || High-end Performance || [[octa-core|Octa]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
 
|-
 
|-
−
| [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || High-end Performance || ? ||  
+
| [[File:core i9 logo (2015).png|50px|link=intel/core_i9]] || {{intel|Core i9}} || Ultra Performance || [[deca-core|Deca]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
 
|}
 
|}
  
 
== Release Dates ==
 
== Release Dates ==
−
Comet Lake is expected to be released in mid-2019.
+
Comet Lake processors were introduced in a number of phases. Initial mobile processors were launched on August 21, 2019. Intel followed up with the remaining desktop parts on April 30, 2020. Enterprise and vPro models were followed on May 13, 2020.
  
−
== Compatibility==
+
== Compatibility ==
−
{{empty section}}
+
There are no official drivers by Intel for [[Windows 7]] or [[Windows 8]]. [[Microsoft]] announced that only [[Windows 10]] will have support for Kaby Lake. [[Linux]] added initial support for Kaby Lake starting with Linux Kernel 4.5.
 +
 
 +
{| class="wikitable"
 +
! Vendor !! OS  !! Version !! Notes
 +
|-
 +
| rowspan="4" | [[Microsoft]] || rowspan="4" | Windows || style="background-color: #ffdad6;" | Windows 7 || No Support
 +
|-
 +
| style="background-color: #ffdad6;" | Windows 8 || No Support
 +
|-
 +
| style="background-color: #d6ffd8;" | Windows 10 || Support
 +
|-
 +
| style="background-color: #d6ffd8;" | Windows 11 || Support
 +
|-
 +
| Linux || Linux || style="background-color: #d6ffd8;" | Kernel 4.5 || Initial Support (Fedora 24, Yocto v2.2, ..)
 +
|-
 +
| Google || Chromium || style="background-color: #d6ffd8;" | Chromium || Support
 +
|-
 +
| Wind River || VxWorks || style="background-color: #d6ffd8;" | VxWorks 7 || Support
 +
|}
  
 
== Compiler support ==
 
== Compiler support ==
Line 125: Line 141:
  
 
=== CPUID ===
 
=== CPUID ===
−
{{empty section}}
+
{{further|intel/cpuid|l1=Intel CPUIDs}}
 +
{| class="wikitable tc1 tc2 tc3 tc4 tc5"
 +
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model !! Stepping
 +
|-
 +
| rowspan="2" | {{intel|Comet Lake U|U|l=core}} || 0 || 0x6 || 0x8 || 0xE || 0xC
 +
|-
 +
| colspan="5" | Family 6 Model 142 Stepping 12
 +
|-
 +
| rowspan="2" | {{intel|Comet Lake S|S|l=core}}/{{intel|Comet Lake H|H|l=core}} || 0 || 0x6 || 0xA || 0x5 || 0x0-0x5
 +
|-
 +
| colspan="5" | Family 6 Model 165 Stepping 0-5<br>Stepping: G0=0, P0=1, R1=2, G1=3, P1=4, Q0=5
 +
|}
  
 
== Architecture ==
 
== Architecture ==
 
=== Key changes from {{\\|Coffee Lake}}===
 
=== Key changes from {{\\|Coffee Lake}}===
 +
* Enhanced "14nm++" process results in higher turbo frequencies
 +
 +
* System Architecture
 +
** 25% more [[cores]] (up to 10, from 8)
 +
** 25% more [[last level cache]] (up to 20 MiB, up from 16 MiB)
 +
 +
* Chipset
 +
** {{intel|Cannon Point|300 Series chipset|l=chipset}} → {{intel|Canon Point|400 Series chipset|l=chipset}}
 +
*** 2.5G Ethernet (Foxville) support
 +
*** IntegratedWiFi 6 AX201 (GiG+) support via {{intel|CNVi}}
 +
 +
* Memory
 +
** Faster memory for mainstream desktops (i.e., {{intel|Comet  Lake S|l=core}}) DDR4-2933 (from DDR4-2666)
 +
 +
* Graphics
 +
** {{intel|Gen 9.5|l=arch}} GPUs (No Change)
 +
 +
* Packaging
 +
** [[Die thinning]] on top-end SKUs for better heat removal
 +
 +
{{expand list}}
 +
 +
=== Block Diagram ===
 
{{empty section}}
 
{{empty section}}
 +
 +
==== Gen9.5 ====
 +
See {{intel|Gen9.5#Gen9.5|l=arch}}.
 +
 +
=== Memory Hierarchy ===
 +
The overall memory structure is identical to {{\\|Skylake}}.
 +
 +
<!-- ===================== START IF YOU CHANGE HERE, CHANGE ON SKYLAKE !! ============================= -->
 +
* Cache
 +
** L0 µOP cache:
 +
*** 1,536 µOPs, 8-way set associative
 +
**** 32 sets, 6-µOP line size
 +
**** statically divided between threads, per core, inclusive with L1I
 +
** L1I Cache:
 +
*** 32 [[KiB]], 8-way set associative
 +
**** 64 sets, 64 B line size
 +
**** shared by the two threads, per core
 +
** L1D Cache:
 +
*** 32 KiB, 8-way set associative
 +
*** 64 sets, 64 B line size
 +
*** shared by the two threads, per core
 +
*** 4 cycles for fastest load-to-use (simple pointer accesses)
 +
**** 5 cycles for complex addresses
 +
*** 64 B/cycle load bandwidth
 +
*** 32 B/cycle store bandwidth
 +
*** Write-back policy
 +
** L2 Cache:
 +
*** Unified, 256 KiB, 4-way set associative
 +
*** Non-inclusive
 +
*** 1024 sets, 64 B line size
 +
*** 12 cycles for fastest load-to-use
 +
*** 64 B/cycle bandwidth to L1$
 +
*** Write-back policy
 +
** L3 Cache/LLC:
 +
*** Up to 2 MiB Per core, shared across all cores
 +
*** Up to 16-way set associative
 +
*** Inclusive
 +
*** 64 B line size
 +
*** Write-back policy
 +
*** Per each core:
 +
**** Read: 32 B/cycle (@ ring [[clock]])
 +
**** Write: 32 B/cycle (@ ring clock)
 +
*** 42 cycles for fastest load-to-use
 +
** Side Cache:
 +
*** 64 MiB & 128 MiB [[eDRAM]]
 +
*** Per package
 +
*** Only on the Iris Pro GPUs
 +
*** Read: 32 B/cycle (@ [[eDRAM]] clock)
 +
*** Write: 32 B/cycle (@ eDRAM clock)
 +
** System [[DRAM]]:
 +
*** 2 Channels
 +
*** 8 B/cycle/channel (@ memory clock)
 +
*** 42 cycles + 51 ns latency
 +
 +
Coffee Lake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).
 +
* TLBs:
 +
** ITLB
 +
*** 4 KiB page translations:
 +
**** 128 entries; 8-way set associative
 +
**** dynamic partitioning
 +
*** 2 MiB / 4 MiB page translations:
 +
**** 8 entries per thread; fully associative
 +
**** Duplicated for each thread
 +
** DTLB
 +
*** 4 KiB page translations:
 +
**** 64 entries; 4-way set associative
 +
**** fixed partition
 +
*** 2 MiB / 4 MiB page translations:
 +
**** 32 entries; 4-way set associative
 +
**** fixed partition
 +
*** 1G page translations:
 +
**** 4 entries; 4-way set associative
 +
**** fixed partition
 +
** STLB
 +
*** 4 KiB + 2 MiB page translations:
 +
**** 1536 entries; 12-way set associative
 +
**** fixed partition
 +
*** 1 GiB page translations:
 +
**** 16 entries; 4-way set associative
 +
**** fixed partition
 +
<!-- ===================== END IF YOU CHANGE HERE, CHANGE ON SKYLAKE !! ============================= -->
 +
 +
 +
* '''Note:''' STLB is incorrectly reported as "6-way" by CPUID leaf 2 (EAX=02H). Coffee Lake erratum CFL084 recommends software to simply ignore that value.
 +
 +
== Overview ==
 +
{{empty section}}
 +
 +
== Configurability ==
 +
{{empty section}}
 +
 +
== Graphics ==
 +
{{empty section}}
 +
 +
== Die ==
 +
{{empty section}}
 +
 +
== All Comet Lake Chips ==
 +
<!-- NOTE:
 +
          This table is generated automatically from the data in the actual articles.
 +
          If a microprocessor is missing from the list, an appropriate article for it needs to be
 +
          created and tagged accordingly.
 +
 +
          Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
 +
-->
 +
{{comp table start}}
 +
<table class="comptable sortable tc7 tc8 tc20 tc21">
 +
{{comp table header|main|20:List of Comet Lake-based Processors}}
 +
{{comp table header|main|9:Main processor|2:Frequencies|Memory|3:GPU|2:Features}}
 +
{{comp table header|cols|Launched|Price|Family|Platform|Core|Cores|Threads|L3$|TDP|Base|Max Turbo|Max Memory|Name|Base|Burst|{{intel|TBT}}|{{intel|Hyper-Threading|HT}}}}
 +
{{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Comet Lake]]
 +
|?full page name
 +
|?model number
 +
|?first launched
 +
|?release price
 +
|?microprocessor family
 +
|?platform
 +
|?core name
 +
|?core count
 +
|?thread count
 +
|?l3$ size
 +
|?tdp
 +
|?base frequency#GHz
 +
|?turbo frequency (1 core)#GHz
 +
|?max memory#GiB
 +
|?integrated gpu
 +
|?integrated gpu base frequency
 +
|?integrated gpu max frequency
 +
|?has intel turbo boost technology 2_0
 +
|?has simultaneous multithreading
 +
|format=template
 +
|template=proc table 3
 +
|userparam=19:20
 +
|mainlabel=-
 +
|limit=200
 +
}}
 +
{{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::CometLake]]}}
 +
</table>
 +
{{comp table end}}

Latest revision as of 17:48, 13 September 2022

Edit Values
Comet Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Process14 nm
Core Configs4
Pipeline
TypeSuperscalar, Superpipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Decode5-way
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache256 KiB/core
4-way set associative
L3 Cache2 MiB/core
Up to 16-way set associative
L4 Cache128 MiB/package
on Iris Pro GPUs only
Cores
Core NamesComet Lake U,
Comet Lake S
Succession

Comet Lake (CML) is Intel's successor to Coffee Lake, an enhanced 14 nm process microarchitecture for mainstream desktops and mobile devices.

For desktop and mobile, Comet Lake is branded as 10th Generation Intel Core i3, Core i5, Core i7, and Core i9 processors.

Codenames[edit]

Core Abbrev Description Graphics Target
Comet Lake S CML-S Mainstream performance GT2 Desktop performance to value, AiOs, and minis
Comet Lake U CML-U Ultra-low power GT2 Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room

Brands[edit]

Intel has released Comet Lake under 4 main brand families:

Logo Family General Description Differentiating Features
Cores HT AVX AVX2 TBT ECC
core i3 logo (2015).png Core i3 Low-end Performance Quad ✔ ✔ ✔ ✔ ✘
core i5 logo (2015).png Core i5 Mid-range Performance Hexa ✔ ✔ ✔ ✔ ✘
core i7 logo (2015).png Core i7 High-end Performance Octa ✔ ✔ ✔ ✔ ✘
50px Core i9 Ultra Performance Deca ✔ ✔ ✔ ✔ ✘

Release Dates[edit]

Comet Lake processors were introduced in a number of phases. Initial mobile processors were launched on August 21, 2019. Intel followed up with the remaining desktop parts on April 30, 2020. Enterprise and vPro models were followed on May 13, 2020.

Compatibility[edit]

There are no official drivers by Intel for Windows 7 or Windows 8. Microsoft announced that only Windows 10 will have support for Kaby Lake. Linux added initial support for Kaby Lake starting with Linux Kernel 4.5.

Vendor OS Version Notes
Microsoft Windows Windows 7 No Support
Windows 8 No Support
Windows 10 Support
Windows 11 Support
Linux Linux Kernel 4.5 Initial Support (Fedora 24, Yocto v2.2, ..)
Google Chromium Chromium Support
Wind River VxWorks VxWorks 7 Support

Compiler support[edit]

Compiler Arch-Specific Arch-Favorable
ICC -march=skylake -mtune=skylake
GCC -march=skylake -mtune=skylake
LLVM -march=skylake -mtune=skylake
Visual Studio /arch:AVX2 /tune:skylake

CPUID[edit]

Further information: Intel CPUIDs
Core Extended
Family 		Family Extended
Model 		Model Stepping
U 0 0x6 0x8 0xE 0xC
Family 6 Model 142 Stepping 12
S/H 0 0x6 0xA 0x5 0x0-0x5
Family 6 Model 165 Stepping 0-5
Stepping: G0=0, P0=1, R1=2, G1=3, P1=4, Q0=5

Architecture[edit]

Key changes from Coffee Lake[edit]

  • Enhanced "14nm++" process results in higher turbo frequencies
  • System Architecture
  • Memory
    • Faster memory for mainstream desktops (i.e., Comet Lake S) DDR4-2933 (from DDR4-2666)
  • Packaging

This list is incomplete; you can help by expanding it.

Block Diagram[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Gen9.5[edit]

See Gen9.5#Gen9.5.

Memory Hierarchy[edit]

The overall memory structure is identical to Skylake.

  • Cache
    • L0 µOP cache:
      • 1,536 µOPs, 8-way set associative
        • 32 sets, 6-µOP line size
        • statically divided between threads, per core, inclusive with L1I
    • L1I Cache:
      • 32 KiB, 8-way set associative
        • 64 sets, 64 B line size
        • shared by the two threads, per core
    • L1D Cache:
      • 32 KiB, 8-way set associative
      • 64 sets, 64 B line size
      • shared by the two threads, per core
      • 4 cycles for fastest load-to-use (simple pointer accesses)
        • 5 cycles for complex addresses
      • 64 B/cycle load bandwidth
      • 32 B/cycle store bandwidth
      • Write-back policy
    • L2 Cache:
      • Unified, 256 KiB, 4-way set associative
      • Non-inclusive
      • 1024 sets, 64 B line size
      • 12 cycles for fastest load-to-use
      • 64 B/cycle bandwidth to L1$
      • Write-back policy
    • L3 Cache/LLC:
      • Up to 2 MiB Per core, shared across all cores
      • Up to 16-way set associative
      • Inclusive
      • 64 B line size
      • Write-back policy
      • Per each core:
        • Read: 32 B/cycle (@ ring clock)
        • Write: 32 B/cycle (@ ring clock)
      • 42 cycles for fastest load-to-use
    • Side Cache:
      • 64 MiB & 128 MiB eDRAM
      • Per package
      • Only on the Iris Pro GPUs
      • Read: 32 B/cycle (@ eDRAM clock)
      • Write: 32 B/cycle (@ eDRAM clock)
    • System DRAM:
      • 2 Channels
      • 8 B/cycle/channel (@ memory clock)
      • 42 cycles + 51 ns latency

Coffee Lake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).

  • TLBs:
    • ITLB
      • 4 KiB page translations:
        • 128 entries; 8-way set associative
        • dynamic partitioning
      • 2 MiB / 4 MiB page translations:
        • 8 entries per thread; fully associative
        • Duplicated for each thread
    • DTLB
      • 4 KiB page translations:
        • 64 entries; 4-way set associative
        • fixed partition
      • 2 MiB / 4 MiB page translations:
        • 32 entries; 4-way set associative
        • fixed partition
      • 1G page translations:
        • 4 entries; 4-way set associative
        • fixed partition
    • STLB
      • 4 KiB + 2 MiB page translations:
        • 1536 entries; 12-way set associative
        • fixed partition
      • 1 GiB page translations:
        • 16 entries; 4-way set associative
        • fixed partition


  • Note: STLB is incorrectly reported as "6-way" by CPUID leaf 2 (EAX=02H). Coffee Lake erratum CFL084 recommends software to simply ignore that value.

Overview[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Configurability[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Graphics[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Die[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

All Comet Lake Chips[edit]

 List of Comet Lake-based Processors
 Main processorFrequenciesMemoryGPUFeatures
ModelLaunchedPriceFamilyPlatformCoreCoresThreadsL3$TDPBaseMax TurboMax MemoryNameBaseBurstTBTHT
Count: 0
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/comet_lake&oldid=100502"
Facts about "Comet Lake - Microarchitectures - Intel"
RDF feed
codenameComet Lake +
core count4 +
designerIntel +
full page nameintel/microarchitectures/comet lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameComet Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process14 nm (0.014 μm, 1.4e-5 mm) +