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KaisHeng KH-25800
KH-25800 front
General Info
Designer	Zhaoxin
Manufacturer	HLMC
Model Number	KH-25800
Part Number	KH-25800
Market	Server, Networking, Embedded
Introduction	December 28, 2017 (announced) December 28, 2017 (launched)
General Specs
Family	KaisHeng
Series	KH-20000
Frequency	1,800 MHz
Bus type	PCIe 3.0
Bus rate	4 × 8 GT/s
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	WuDaoKou
Process	28 nm
Transistors	2,100,000,000
Technology	CMOS
Die	187 mm²
Word Size	64 bit
Cores	8
Threads	8
Max Memory	128 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Tjunction	0 °C – 90 °C

KaisHeng KH-25800 is a 64-bit octa-core x86 microprocessor designed by Zhaoxin and introduced in late 2017 specifically for the Chinese market. This processor is fabricated on a 28 nm process based on the WuDaoKou microarchitecture. The KH-25800 operates at 1.8 GHz with a TDP of ? W and supports up to 128 GiB of dual-channel DDR4-2133 ECC memory.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: WuDaoKou § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 512 KiB 524,288 B 0.5 MiB L1I$ 256 KiB 262,144 B 0.25 MiB 8x32 KiB 8-way set associative   L1D$ 256 KiB 262,144 B 0.25 MiB 8x32 KiB 8-way set associative   L2$ 8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB     2x4 MiB 32-way set associative

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2133 Supports ECC Yes Max Mem 128 GiB Controllers 1 Channels 2 Max Bandwidth 31.79 GiB/s 32,552.96 MiB/s 34.134 GB/s 34,134.253 MB/s 0.031 TiB/s 0.0341 TB/s Bandwidth Single 15.89 GiB/s Double 31.79 GiB/s

Expansions

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	Expansion Options
PCIe Revision: 3.0 Max Lanes: 24

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 AES AES Encryption Instructions RdRand Hardware RNG SHA SHA Extensions x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute TXT Trusted Execution Technology (SMX) VT-x VT-x (Virtualization) EPT Extended Page Tables (SLAT)