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Kirin 810 - HiSilicon
Edit Values | |
Kirin 810 | |
General Info | |
Designer | HiSilicon, ARM Holdings |
Manufacturer | TSMC |
Model Number | 810 |
Market | Mobile |
Introduction | June 21, 2019 (announced) June 21, 2019 (launched) |
General Specs | |
Family | Kirin |
Series | 800 |
Frequency | 2,270 MHz, 1,880 MHz |
Microarchitecture | |
ISA | ARMv8 (ARM) |
Microarchitecture | Cortex-A76, Cortex-A55 |
Core Name | Cortex-A76, Cortex-A55 |
Process | 7 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 8 |
Threads | 8 |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Succession | |
Kirin 810 is a 64-bit octa-core mid-range performance mobile ARM SoC introduced by HiSilicon in mid-2019. This chip, which is fabricated on TSMC's 7 nm process, features two Cortex-A76 big cores operating at up to 2.27 GHz along with six Cortex-A55 little cores operating at up to 1.88 GHz. The 810 incorporates ARM's Mali-G52 MP6 GPU.
Contents
Cache[edit]
- Main articles: Cortex-A55 § Cache and Cortex-A76 § Cache
For the Cortex-A76:
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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For the Cortex-A55:
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Graphics[edit]
Integrated Graphics Information
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- Hardware Acceleration
- Decode: 1080p @ 60fps
- Encode: 1080p @ 30fps
NPU[edit]
This is the first neural processing unit to use their own homegrown NPU based on Hisilicon's first generation Da Vinci architecture. The NPU contains one processor core and a scheduling core.
ISP[edit]
- 40 MP+ 24 MP dual
48 single
Wireless[edit]
- LTE Modem
- DL: Up to User Equipment (UE) category 12
- Downlink of up to 600 Mbps
- UL: Up to User Equipment (UE) category 13
- Uplink of up to 200 Mbps (2x2 MIMO, 256-QAM, 1x20MHz CA)
- DL: Up to User Equipment (UE) category 12
- Wi-Fi 802.11 ac
- Bluetooth 5
- NFC
- GPS / A-GPS / GLONASS / BDS
Location[edit]
- GPS, AGPS, Glonass, Beidou
Utilizing devices[edit]
- Huawei Nova 5
- Huawei Honor 9x
- Huawei Honor 9x Pro
- Huawei Mate 30 Lite
- Huawei P40 Lite
- Huawei Nova 7i
- Huawei nova 6 SE
- Huawei P smart Pro 2019
- Huawei nova 5z
- Huawei nova 5i Pro
- Huawei Honor 20S
- Huawei MatePad 10.4
Categories:
- all microprocessor models
- microprocessor models by hisilicon
- microprocessor models by hisilicon based on cortex-a76
- microprocessor models by hisilicon based on cortex-a55
- microprocessor models by arm holdings
- microprocessor models by arm holdings based on cortex-a76
- microprocessor models by arm holdings based on cortex-a55
- microprocessor models by tsmc
Facts about "Kirin 810 - HiSilicon"
base frequency | 2,270 MHz (2.27 GHz, 2,270,000 kHz) + and 1,880 MHz (1.88 GHz, 1,880,000 kHz) + |
core count | 8 + |
core name | Cortex-A76 + and Cortex-A55 + |
designer | HiSilicon + and ARM Holdings + |
family | Kirin + |
first announced | June 21, 2019 + |
first launched | June 21, 2019 + |
full page name | hisilicon/kirin/810 + |
has ecc memory support | false + |
instance of | microprocessor + |
integrated gpu | Mali-G52 + |
integrated gpu base frequency | 850 MHz (0.85 GHz, 850,000 KHz) + |
integrated gpu designer | ARM Holdings + |
integrated gpu execution units | 6 + |
isa | ARMv8 + |
isa family | ARM + |
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + and 384 KiB (393,216 B, 0.375 MiB) + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + and 192 KiB (196,608 B, 0.188 MiB) + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + and 192 KiB (196,608 B, 0.188 MiB) + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + and 0.75 MiB (768 KiB, 786,432 B, 7.324219e-4 GiB) + |
ldate | June 21, 2019 + |
manufacturer | TSMC + |
market segment | Mobile + |
max cpu count | 1 + |
max memory bandwidth | 31.78 GiB/s (32,542.72 MiB/s, 34.124 GB/s, 34,123.515 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 4 + |
microarchitecture | Cortex-A76 + and Cortex-A55 + |
model number | 810 + |
name | Kirin 810 + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + |
series | 800 + |
smp max ways | 1 + |
supported memory type | LPDDR4X-4266 + |
technology | CMOS + |
thread count | 8 + |
used by | Huawei Nova 5 +, Huawei Honor 9x +, Huawei Honor 9x Pro +, Huawei Mate 30 Lite +, Huawei P40 Lite +, Huawei Nova 7i +, Huawei nova 6 SE +, Huawei P smart Pro 2019 +, Huawei nova 5z +, Huawei nova 5i Pro +, Huawei Honor 20S + and Huawei MatePad 10.4 + |
word size | 64 bit (8 octets, 16 nibbles) + |