From WikiChip
Kunpeng 920-4826 - HiSilicon
| Edit Values | |
| Kunpeng 920-4826 | |
| General Info | |
| Designer | HiSilicon, ARM Holdings |
| Manufacturer | TSMC |
| Model Number | 920-4826 |
| Market | Server |
| Introduction | April 26, 2019 (announced) April 26, 2019 (launched) |
| General Specs | |
| Family | Hi16xx |
| Series | 920 |
| Frequency | 2,600 MHz |
| Microarchitecture | |
| ISA | ARMv8.2 (ARM) |
| Microarchitecture | TaiShan v110 |
| Core Name | TaiShan v110 |
| Transistors | 20,000,000,000 |
| Technology | CMOS |
| MCP | Yes (3 dies) |
| Word Size | 64 bit |
| Cores | 48 |
| Threads | 48 |
| Max Memory | 1 TiB |
| Multiprocessing | |
| Max SMP | 4-Way (Multiprocessor) |
| Electrical | |
| TDP | 158 W |
Kunpeng 920-4826 is a octatetraconta-core 64-bit ARM server microprocessor introduced by HiSilicon in early 2019. Fabricated by TSMC on a 7nm HPC process based on the TaiSHan v110 microarchitecture, this chip incorporates 48 cores operating at 2.6 GHz with a TDP of 150 W. This chip supports up to 1 TiB of octa-channel DDR4-2933 memory.
Cache[edit]
- Main article: TaiShan v110 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
Expansion Options |
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Features[edit]
[Edit/Modify Supported Features]
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Supported ARM Extensions & Processor Features
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Utilizing devices[edit]
- HiSilicon D06
- TaiShan 5280
- TaiShan 5290
- TaiShan X6000
This list is incomplete; you can help by expanding it.
Facts about "Kunpeng 920-4826 - HiSilicon"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Kunpeng 920-4826 - HiSilicon#pcie + |
| base frequency | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + |
| core count | 48 + |
| core name | TaiShan v110 + |
| designer | HiSilicon + and ARM Holdings + |
| die count | 3 + |
| family | Hi16xx + |
| first announced | April 26, 2019 + |
| first launched | April 26, 2019 + |
| full page name | hisilicon/kunpeng/920-4826 + |
| has ecc memory support | true + |
| instance of | microprocessor + |
| is multi-chip package | true + |
| isa | ARMv8.2 + |
| isa family | ARM + |
| l1$ size | 6,144 KiB (6,291,456 B, 6 MiB) + |
| l1d$ size | 3,072 KiB (3,145,728 B, 3 MiB) + |
| l1i$ size | 3,072 KiB (3,145,728 B, 3 MiB) + |
| l2$ size | 24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) + |
| l3$ size | 48 MiB (49,152 KiB, 50,331,648 B, 0.0469 GiB) + |
| ldate | April 26, 2019 + |
| main image | |
| manufacturer | TSMC + |
| market segment | Server + |
| max cpu count | 4 + |
| max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
| max memory bandwidth | 190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) + |
| max memory channels | 8 + |
| max sata ports | 2 + |
| max usb ports | 4 + |
| microarchitecture | TaiShan v110 + |
| model number | 920-4826 + |
| name | Kunpeng 920-4826 + |
| series | 920 + |
| smp max ways | 4 + |
| supported memory type | DDR4-2933 + |
| tdp | 158 W (158,000 mW, 0.212 hp, 0.158 kW) + |
| technology | CMOS + |
| thread count | 48 + |
| transistor count | 20,000,000,000 + |
| used by | HiSilicon D06 +, TaiShan 5280 +, TaiShan 5290 + and TaiShan X6000 + |
| word size | 64 bit (8 octets, 16 nibbles) + |