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Cooper Lake - Microarchitectures - Intel
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Cooper Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionJune 18, 2020
Process14 nm
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache1 MiB/core
16-way set associative
L3 Cache1.375 MiB/core
11-way set associative
Cores
Core NamesCooper Lake X,
Cooper Lake SP,
Cooper Lake AP
Succession
Contemporary
Coffee Lake

Cooper Lake (CPL) is Intel's successor to Cascade Lake, a 14 nm microarchitecture for enthusiasts and servers.

Launched in mid-2020, Cooper Lake covers the 4-way and 8-way multiprocessing segments while Ice Lake serves the single and dual-socket segments.

For scalable server class processors, Intel branded it as Xeon Gold and Xeon Platinum.

Codenames[edit]

Core Abbrev Target
Cooper Lake X CPL-X High-end desktops & enthusiasts market
Cooper Lake W CPL-W Enterprise/Business workstations
Cooper Lake SP CPL-SP Server Scalable Processors
Cooper Lake AP CPL-AP Server Advanced Processors

Brands[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Release Dates[edit]

Cooper Lake and Ice Lake roadmap.

Cooper Lake launched on June 18, 2020.

Process Technology[edit]

Cooper Lake is fabricated on Intel's 3rd generation enhanced 14nm++ process.

Architecture[edit]

Key changes from Cascade Lake[edit]

  • SoC
    • 2x UPI links (6, up from 3)
  • Memory
    • Higher data rate (3200 MT/s, up from 2933 MT/s)
    • Optane DC DIMMs
      • Apache Pass Barlow Pass
  • Packaging
    • Socket-P+
      • 4189-contact flip-chip LGA (up from 3647 contacts)

This list is incomplete; you can help by expanding it.

New instructions[edit]

Cooper Lake introduced a number of new instructions:

See also[edit]

codenameCooper Lake +
designerIntel +
first launchedJune 18, 2020 +
full page nameintel/microarchitectures/cooper lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameCooper Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process14 nm (0.014 μm, 1.4e-5 mm) +