Semiconductor & Computer Engineering
From WikiChip
CN5734-1000 SP - Cavium
| Edit Values | |||||||||
| Cavium CN5734-1000 SP | |||||||||
 | |||||||||
| General Info | |||||||||
| Designer | Cavium | ||||||||
| Manufacturer | TSMC | ||||||||
| Model Number | CN5734-1000 SP | ||||||||
| Part Number | CN5734-1000BG1217-SP | ||||||||
| Market | Storage | ||||||||
| Introduction | Jun 26, 2007 (announced) August, 2007 (launched) | ||||||||
| General Specs | |||||||||
| Family | OCTEON Plus | ||||||||
| Series | CN57xx | ||||||||
| Frequency | 1,000 MHz | ||||||||
| Microarchitecture | |||||||||
| ISA | MIPS64 (MIPS) | ||||||||
| Microarchitecture | cnMIPS | ||||||||
| Process | 90 nm | ||||||||
| Technology | CMOS | ||||||||
| Word Size | 64 bit | ||||||||
| Cores | 6 | ||||||||
| Threads | 6 | ||||||||
| Multiprocessing | |||||||||
| Max SMP | 1-Way (Uniprocessor) | ||||||||
| Packaging | |||||||||
| |||||||||
CN5734-1000 SP is a 64-bit hexa-core MIPS storage processor (SP) designed by Cavium and introduced in 2007. This processor, which incorporates six cnMIPS cores, operates at 1 GHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, networking, TCP & QoS acceleration.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
 |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||
|
|||||||||||||||||||||||||
Memory controller[edit]
 |
Integrated Memory Controller
|
|||||||||||||
|
||||||||||||||
Expansions[edit]
 |
Expansion Options
|
|||||||||||
|
||||||||||||
Networking[edit]
Interface options:
- 8-lanes PCIe + 8-lanes PCIe
- 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
- 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]
 |
Networking
|
|||||
|
||||||
Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
 |
Hardware Accelerators
|
|||||||||||||||||
|
||||||||||||||||||
Block diagram[edit]
Datasheet[edit]
Facts about "CN5734-1000 SP - Cavium"
