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CN5745-800 SP - Cavium
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Cavium CN5745-800 SP
Octeon CN57xx.svg
General Info
DesignerCavium
ManufacturerTSMC
Model NumberCN5745-800 SP
Part NumberCN5745-800BG1217-SP
MarketStorage
IntroductionJun 26, 2007 (announced)
August, 2007 (launched)
General Specs
FamilyOCTEON Plus
SeriesCN57xx
Frequency800 MHz
Microarchitecture
ISAMIPS64 (MIPS)
MicroarchitecturecnMIPS
Process90 nm
TechnologyCMOS
Word Size64 bit
Cores10
Threads10
Max CPUs1 (Uniprocessor)
Packaging
PackageFCBGA-1217 (BGA)
Dimension40 mm x 40 mm
Ball Count1217
InterconnectBGA-1217

CN5745-800 SP is a 64-bit deca-core MIPS storage processor (SP) designed by Cavium and introduced in 2007. This processor, which incorporates ten cnMIPS cores, operates at 800 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, networking, TCP & QoS acceleration.

Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$480 KiB
0.469 MiB
491,520 B
4.577637e-4 GiB
L1I$320 KiB
0.313 MiB
327,680 B
3.051758e-4 GiB
10x32 KiB  
L1D$160 KiB
0.156 MiB
163,840 B
1.525879e-4 GiB
10x16 KiB  

L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-800
Supports ECCYes
Controllers1
Channels2
Width64 bit
Max Bandwidth11.92 GiB/s
Bandwidth
Single 5.96 GiB/s
Double 11.92 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision1.0
Max Lanes8
Configsx4, x8
UART

GP I/OYes

Networking[edit]

Interface options:

  • 8-lanes PCIe + 8-lanes PCIe
  • 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
  • 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
XAUIYes (Ports: 1)
SGMIIYes (Ports: 4)

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
Networking
TCPYes
QoSYes
Compression
CompressionYes
DecompressionYes
RAID
RAID 5Yes
RAID 6Yes

Block diagram[edit]

cn57xx block diagram.png

Datasheet[edit]

Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
CN5745-800 SP - Cavium#package +
base frequency800 MHz (0.8 GHz, 800,000 kHz) +
core count10 +
designerCavium +
familyOCTEON Plus +
first announcedJune 26, 2007 +
first launchedAugust 2007 +
full page namecavium/octeon plus/cn5745-800bg1217-sp +
has ecc memory supporttrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
has hardware raid 5 supporttrue +
has hardware raid 6 supporttrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size0.469 MiB (480 KiB, 491,520 B, 4.577637e-4 GiB) +
l1d$ size0.156 MiB (160 KiB, 163,840 B, 1.525879e-4 GiB) +
l1i$ size0.313 MiB (320 KiB, 327,680 B, 3.051758e-4 GiB) +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldateAugust 2007 +
main imageFile:Octeon CN57xx.svg +
manufacturerTSMC +
market segmentStorage +
max cpu count1 +
max memory channels2 +
max pcie lanes8 +
microarchitecturecnMIPS +
model numberCN5745-800 SP +
nameCavium CN5745-800 SP +
packageFCBGA-1217 +
part numberCN5745-800BG1217-SP +
process90 nm (0.09 μm, 9.0e-5 mm) +
seriesCN57xx +
supported memory typeDDR2-800 +
technologyCMOS +
thread count10 +
word size64 bit (8 octets, 16 nibbles) +