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ARM1 µarch
General Info
Arch Type	CPU
Designer	Acorn Computers
Manufacturer	VLSI Technology
Introduction	1985
Process	3 µm
Core Configs	1
Pipeline
Type	Scalar, Pipelined
Stages	3
Decode	1-way
Instructions
ISA	ARMv1
Cache
L1I Cache	0 KiB/Core
L1D Cache	0 KiB/Core
Succession
ARM2

ARM1 was the first ARM microarchitecture implemented by Acorn Computers as a research and development project for the BBC Computer Literacy Project. ARM1 was introduced in 1985 and was extended to be used as a coprocessor in the Acorn's BBC Micro microcomputers. ARM1 was distributed as an evaluation system and was never commercialized.

History

Main article: ARM's History

The ARM1 (Acorn RISC Machine 1) is Acorn Computers' first microprocessor design. The ARM1 was the initial result of the Advanced Research and Development division Acorn Computers formed in order to advance the development of their own RISC processor. The ARM instruction set design started in 1983. A reference model was written in BBC BASIC by Sophie Wilson and Steve Furber in just 808 lines of code. On April 26 1985, after 6 man-years of design effort, the first ARM processor prototype was delivered. The first batch of prototypes were functional and were shipped to customers in the form of evaluation systems. At that time the ARM1 was the simplest RISC processor produced.

The first prototype tested worked on the first try, this was despite the ammeter reading no power. The prototype test board designed was faulty with a short. The chip was entirely running off the leakage from the I/Os. Designed to run at 1 W, the chip averaged under 100 mW typical power.

Originally intended to perform at roughly 1.5 times performance of the VAX 11/780, the prototypes ended up achieveing between 2x to 4x the performance of the DEC VAX 11/780; this is roughly equivalent to 10 times that of that original IBM PC AT or that of the Motorola 68020 operating at 16.67 MHz.

Process Technology

See also: 3 µm process

ARM1 chips were manufactured by VLSI Technology on a 3 µm double-level metal CMOS process.

Architecture

The ARM1 is based on the ARMv1 ISA which is an entirely clean-sheet 32-bit RISC design.

Overview

• 3 µm process
• Implements ARMv1
• Goal 1.5x performance of the VAX 11/780
• 26-bit address space
• Pipeline
  • Very simple
  • 3-stage
  • No hardware multiplication
  • 25 32-bit registers
    • 16 For user
    • 9 For supervisor
  • 4 Modes
    • User, Supervisor, IRQ, FIQ

Block Diagram

Core

Core

The ARM1 is an extremely simple 32-bit single-chip RISC microprocessor implementation with a number of CISC features.

Pipeline

The ARM1 utilizes a pipelining technique in order to improve performance and efficiency. At peak performance the ARM1 can reach 8 million instructions per second with an average of 3 MIPS when using a 150 ns row access DRAM. The ARM1's pipeline consists of 3 stages (although some instructions may take as much as 5 cycles):

The ARM1 operates on a guaranteed non-overlapping two-phase clock which allowed for level-triggered transfer instead of edge-triggering. The two clock phases are not generated on-die but come from an external oscillator. A complete cycle on the ARM1 is therefore Φ1 + Φ2. To simplify system design, these clocks may be stretched to work in-sync with memory access times.

Fetch

The Instruction Pipe is a functional block that holds awaiting instructions until execution, it therefore holds a number of instruction sufficient to ensure instructions are always executing at all cycles on all stages.

The program counter on the ARM1 always points to the instruction being fetched. That is, with every instruction being exactly 4 bytes, the currently executing instruction is always PC - 8. During the fetch stage, the address specified by the address register gets sent through the address pins and is fetched from memory.

In conjunction with the address register is a dedicated incrementer which calculates the next address. The actual address for the next instruction will usually come from that incrementer. However, occasionally, the next instruction may also come from the ALU instead. On very rare occasions, the next instruction value can be forced to an exception. When the instruction is coming from the incrementer, the ARM1 will assert this fact on the SEQ pin, allowing the external memory controller to know that the next instruction will in fact be +4 the current instruction, allowing it to determine if an address translation is necessary and prepare ahead. This is done to improve performance because it can make use of Page-Mode DRAM, allowing for more efficient consecutive memory reads.

Decode

On the second cycle of each instruction, the decode occurs. At this stage the instruction is decoded and the appropriate control signals are generated. The ARM1 implements the decoding in a number of separate units:

• Instruction Decode, performs the top-level decoding
• Register Decode, decodes the register selection field
• ALU Decode, decodes the ALU operation
• Shift Decode, decodes the barrel shifter controls

The Register Decode handles the register selection for both read ports and the write port.

The reason the decode is implemented in a number of separate units is because the ARM1 makes use of microcode ROMs (PLA). Each instruction is decoded into up to four µOP signal-wise. In other words, the ARM instructions are broken down into up to four sets of internal-µOP signals indicating things such as which registers to select or what value to shift by. For some complex operations such as block-transfers, the microsequencer also performs a looping operation for each register.

Execute

The ARM1 has a physical register file of 25 32-bit registers (same as the architectural register file). Register 15 (R15) is the Program Counter. 16 of the registers are visible to the user with the remaining only being accessible while in supervisor mode. The register file has two read ports for the operands heading to the ALU and a single write port for the ALU write-back value. Additionally there is a dedicated R15 read and write port.

Each cycle two values are operated on. During clock phase 1 (Φ1) the values are fetched from the appropriate sources into the ALU for execution and during clock phase 2 (Φ2), the 32-bit ALU output is stored onto the Register File write port.

For a typical register-register operation, the first operand is fetched from the register file on Port 0 directly to the ALU while the second operand is fetched from the register file on Port 1 and through the barrel shifter to the ALU. For a register-immediate operation, the first operand is fetched from the register file on Port 0 directly to the ALU while the second operand is fetched from the instruction.

Register-Register:

Register-Immediate:

It's worth noting that the ARM1 lacked hardware multiplication which meant software had to resort to a software-based solution (e.g., classic Shift-and-Add Multiplication). For example to perform var = x * 5; one could rewrite it as var = x + (x << 2); to achieve the same result without a multiplication operation. The downside for this is that unless it's done for very simple operations (such as this example), software multiplication is horrifically slow.

Interrupt

The ARM1 has fast interrupt capabilities for real-time responses. Exceptions can occur internally or externally to the chip. The average interrupt latency is sub-2 µs with a worst case of sub-6 µs. An interrupt must wait for the currently executing instruction to complete before the interrupt executes. The current instruction completes only when a new instruction starts fetching. When an exception takes place, the processor sets the PC to a specific memory address within the interrupt vector table.

For example, in the case of RESET pin being asserted, the current pipeline gets flushed and the PC is forced to execute from address 0x0.

Multi-Cycle Instruction

A number of ARM instructions cannot be implemented in a single cycle given the limited resources of the ARM1 (i.e., a single ALU and a single shifter). Instructions such as a store STR (store register) requires calculating the effective address before it can store the data. To solve this problem, the ARM1 effectively runs the same instruction through the execute stage two to three times - in the first execute cycle is used to compute the address while the second execute stage the data store.

For example, in the case of a STR R2, [R3, #4], in the first execute cycle the processor will perform Address = R3 + 4. ARM1 will then run another execute stage for this instruction. In the second cycle, ARM1 will generate a DOUT = R2 at the address generate previously and assert the appropriate pins to indicate this is a write.

	ADD	Fetch	Decode	Execute
	STR		Fetch	Decode	Address Calculate	Data Store
	ADD			Fetch		Decode	Execute
	ADD				Fetch		Decode	Execute
	ADD						Fetch	Decode	Execute
	Time

Block-transfer

See also: Block-Transfer Instructions

This section is empty; you can help add the missing info by editing this page.

Die Shot

• 3 µm process
• 24,800 transistors
• ~6,000 gates
• ~7 mm x 7mm
• 50 mm² die size
• PLCC-82 (Plastic leaded chip carrier)
  • 74 signal pins
  • 8 power/ground pins

All ARM1 Chips

	List of ARM1-based Processors
Model	Process	Launched	Frequency	Power Dissipation	Max Memory
VC2588	ARM1	1985	6 MHz 0.006 GHz 6,000 kHz	1 W 1,000 mW 0.00134 hp 0.001 kW	64 MiB 65,536 KiB 67,108,864 B 0.0625 GiB 6.103516e-5 TiB
Count: 1

References

• ARM hardware reference manual, ARM Evaluation System, Acorn OEM Products, August 1986
• Furber, S. B., and A. R. P. Thomas. "ARM3—a study in design for compatibility." Microprocessors and Microsystems 14.6 (1990): 407-415.

Documents

• ARM hardware Reference Manual, ARM Evaluation System, Acorn OEM Products, August 4, 1986.