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AMD Athlon XP-M 1200+
General Info
Designer	AMD
Manufacturer	AMD
Model Number	Athlon XP-M 1200+
Part Number	AXML1200GTS3B
Market	Mobile
Shop	Amazon
General Specs
Family	Athlon XP-M
Frequency	1,000 MHz
Bus type	FSB
Bus speed	100 MHz
Bus rate	200 MT/s
Clock multiplier	10
CPUID	0x681
Microarchitecture
Microarchitecture	K7
Core Name	Thoroughbred
Core Family	6
Core Model	8
Core Stepping	B0
Process	130 nm
Transistors	37,200,000
Technology	CMOS
Die	85 mm² 11.33 mm × 7.47 mm
Word Size	32 bit
Cores	1
Threads	1
Max Memory	4 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Vcore	1.2 V
TDP	16 W
Tjunction	0 °C – 95 °C
Packaging
Package	OPGA-563, UOG 563 (FC-µOPGA)
Dimension	33 mm × 33 mm
Pitch	1.27 mm
Contacts	563
Socket	Socket 563

The Athlon XP-M 1200+ (OPN AXML1200GTS3B) was a 32-bit x86 microprocessor developed by AMD for thin and light mobile and value PCs, a low voltage Athlon XP-M processor in a smaller µPGA package as opposed to mainstream and desktop replacement models. It was based on the K7 microarchitecture, had a 256 KiB on die L2 cache, and operated at 1.0 GHz (10 × FSB frequency; the number in the model name and OPN is a relative performance rating). Its 100 MHz, 64-bit front side bus supported raw data rates up to 1.6 GB/s. The processor was manufactured on a 130 nm copper process at AMD's Fab 30 in Dresden, Germany.

Cache

Main article: K7 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB   2-way set associative   L1D$ 64 KiB 65,536 B 0.0625 MiB   2-way set associative write-allocate, write-back L2$ 256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB       16-way set associative victim cache

Features

[Edit/Modify Supported Features]

	Supported x86 Extensions & Processor Features
	MMX MMX Extension EMMX Extended MMX Extension 3DNow! 3DNow! Extension E3DNow! Extended 3DNow! Extension SSE Streaming SIMD Extensions x86-16 16-bit x86 x86-32 32-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU PowerNow! PowerNow