|isa=x86-64 ...as|Austin]] - [[wikipedia:Mount Bonnell|Mount Bonnell]], was Intel's first x86-compatible [[microarchitecture]] designed to target the ultra-low power mar

|isa=x86-64 Silvermont introduced a number of {{x86|extensions|new instructions}}:

|isa=x86-64 * {{x86|CLMUL}} instructions are now a single [[µOP]], improving latency and throu

|isa=x86-64 ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]

|isa=x86-64 ! Cores !! Unlocked !! {{x86|AVX2}} !! [[SMT]] !! {{amd|XFR}} !! [[IGP]] !! [[ECC]] !! [[Multiprocessin

{{x86 title|Extensions}}{{x86 isa main}} The [[x86]] [[instruction set architecture|ISA]] has gone through numerous iterations

...d that must determine variable length instruction boundaries and translate x86 instructions into internal micro-ops. In contrast, Merced fetches fixed len ...streaming buffer with eight 32-byte entries. Unlike x86 chips, instruction prefetch is controlled by software.

|isa=x86-64 * 8 to 64 {{amd|Zen 3|l=arch}} [[x86]] CPU cores with 2-way [[SMT]]

{{x86 title|Advanced Vector Extensions 512 (AVX-512)}}{{x86 isa main}} ...ber of {{arch|512}} [[SIMD]] [[x86]] [[instruction set]] extensions. The {{x86|extensions}} were formally introduced by [[Intel]] in July [[2013]] with fi

|isa=x86-64 ** Improved cache prefetch

|isa=x86-16 |isa 2=x86-32

...oarchitecture with advanced dynamic branch prediction, 4-way decoding of [[x86]] instructions with a stack optimizer, multiple caches including an Op cach * {{x86|AVX-512}} instructions support, 256-bit data path<ref name="ryzen-7000-prev

|isa=x86-64 * 16 to 96 {{amd|Zen 4|l=arch}} [[x86]] CPU cores with 2-way [[SMT]]

|isa=x86-64 ...aging to OEMs. They identify as members of {{amd|CPUID#Family 25 (19h)|AMD x86 CPU Family 19h, Model 08h}}.