...lly, the process node name referred to a number of different features of a transistor including the [[gate length]] as well as M1 half-pitch. Most recently, due ...l pitch]] (MMP) need to scale by roughly 0.7x each node. In other words, a scaling of <code>0.7x CPP ⋅ 0.7x MMP ≈ ½ area</code>. The node names are effec

...ments. Ivy Bridge became Intel's first microarchitecture to use [[tri-gate transistor]]s for their commercial products. [[Scaling]]:

| process 1 transistor = FinFET | process 2 transistor = FinFET

...size and its technology, and '''does not''' represent any geometry of the transistor. ...PDK update over the one used by Alder Lake, their 3rd generation SuperFin Transistor architecture. Intel says this process brings transistors with significantly

...size and its technology, and '''does not''' represent any geometry of the transistor. ...consists of 60% logic, 30% SRAM, and 10% analog/IO, their 5 nm technology scaling was projected to reduce chip size by 35%-40%.

* Thompson, Scott. "MOS scaling: Transistor challenges for the 21st century." Intel Technology Journal. 1998.

...balance needed between the various competing aspects of a microprocessor - transistor allocation/die size, clock/frequency restriction, power limitations, and ne ...equency tuning, and [[dynamic clocking]]. [[Adaptive voltage and frequency scaling]] (AVFS), an on-die closed-loop system that adjusts the voltage in real tim

...rophecy in the [[semiconductor industry]] that states that the number of [[transistor]]s on a dense [[integrated circuit]] roughly doubles every 24 months. The law is largely a law of economics whereby the scaling of devices allows for more logic to be packed at a lower price. The law has

...ex and is governed by multiple mechanisms that perform [[dynamic frequency scaling]] based on the available headroom. With the {{intel|process|increasing transistor budget}} new features are added and the overall core grows in capabilities.

'''MTr/mm²''' ('''mega-transistor per squared millimeter''') is a [[transistor density]] unit that serves as a [[figure of merit]] in quantifying a [[proc ...y do not represent a typical [[standard cell]]. This metrics estimates the transistor density of an [[integrated circuit]] by filling a square [[die]] with cells

An NRAM cell is largely device-agnostic (both process-agnostic and transistor-agnostic) as well as substrate-agnostic. Once the [[FEOL]] devices are fabr ...te in terms of resistance levels meaning it's limited only by lithography. Scaling down to [[5 nm]] is well understood and it is thought that NRAM can scale d

...contact-to-gate shorts. SAC is [[scaling booster|used to enable aggressive scaling]] of the [[contacted poly pitch]] while minimizing [[yield]] loss due to mi :[[File:cpp scaling.svg|800px]]

{{title|Scaling Booster}} ...beyond classical scaling vectors in order to allow [[Moore's Law]] device scaling to continue or accelerate.

...nMOS and pMOS devices. COAG is [[scaling booster|used to enable aggressive scaling]] of the [[standard cell height]] by moving the gate contact over the activ ...10nm|10-nanometer process node]] in order to achieve a larger-than-normal scaling jump from their prior [[intel 14nm|14-nanometer node]]. Intel reported that

...at the cell boundaries. SDB is [[scaling booster|used to enable aggressive scaling]] of abutting cells without affecting the cell height or underlying devices :[[File:ttt-cell-scaling-sdb.svg|800px]]