Page title matches

• insulated-gate field-effect transistor
  20 bytes (2 words) - 10:53, 14 November 2015

Page text matches

• microprocessor
  ...integrated circuit]] chips in the early 1960s, MOS chips reached higher [[transistor density]] and lower manufacturing costs than [[bipolar]] [[integrated circu ...rds were interconnected in a chassis. The large number of discrete [[logic gate]]s used more electrical power—and therefore produced more heat—than a m
  24 KB (3,399 words) - 11:39, 12 March 2025
• 3 µm lithography process
  | process 1 transistor = Planar | process 1 gate len = 3 µm
  3 KB (314 words) - 23:04, 20 May 2018
• multiplexer
  ...e input from ''A'' should pass to the output while the bottom transmission gate does the same for the ''B'' input. A single [[inverter]] is used to invert A 2:1 MUX can also be built using an [[AOI222]] gate.
  10 KB (1,445 words) - 10:01, 25 October 2025
• buffer gate
  {{title|Buffer Gate}}{{logic gate |title = Buffer Gate
  3 KB (454 words) - 16:15, 11 August 2018
• mosfet
  {{title|MOSFET - Metal-Oxide-Semiconductor Field-Effect-Transistor}} ...e (S) and drain (D) terminals. The gate is separated from the body by an [[gate oxide|insulating layer]] (pink).]]
  193 KB (26,852 words) - 19:51, 11 March 2025
• inverter
  ...ts design onto more complex structures such as [[NOR gate|NOR]] and [[NAND gate|NAND]] gates. The electrical behavior of much bigger and complex circuitry ! colspan="2" | NOT Gate
  6 KB (983 words) - 04:50, 8 November 2015
• 7400 series
  While the original series was designed as [[transistor-transistor logic|TTL]] logic chips, over the years, a large number of sub-families hav ...- When no indicator is found, this implies it's the original [[transistor-transistor logic|TTL]]
  132 KB (19,687 words) - 21:18, 25 October 2025
• cmos
  ...ntary [[mosfet|MOS]] [[transistor]]s - [[pmos transistor|pMOS]] and [[pMOS transistor|nMOS]]. CMOS is the dominant technology used for [[VLSI]] and [[ULSI]] cir ...-MOS'''), is a type of [[MOSFET|metal–oxide–semiconductor field-effect transistor]] (MOSFET) [[semiconductor device fabrication|fabrication process]] that us
  39 KB (5,297 words) - 20:00, 11 March 2025
• bicmos
  ...nalog and digital logic circuits from both [[CMOS]] and [[bipolar junction transistor|Bipolar]] semiconductor technologies. ...ed speed over [[CMOS]] and lower power dissipation than [[bipolar junction transistor|bipolar]] by combining both technologies on a single [[die]]. BiCMOS fabric
  2 KB (329 words) - 08:33, 16 January 2019
• logic gate
  {{confuse|ideal logic gate}} ...emented using discrete components such as [[resistor]]s, [[diode]]s, and [[transistor]]s.
  5 KB (838 words) - 11:19, 10 February 2020
• gate universality
  '''Gate universality''' is a concept that refers to individual [[logic gates]], pri ...t sets of [[pMOS transistor|pMOS]] and [[nMOS transistor|nMOS]] pairs of [[transistor]]s.
  903 bytes (132 words) - 00:34, 8 December 2015
• pass-transistor logic
  ...a class of [[non-restoring logic]] [[logic families|families]] that use [[transistor]]s as switches such that the output [[logic level]]s directly come from the ...ogic with reduced number of active devices thereby producing lower overall transistor count and a reduction in associated interconnections. The obvious drawback
  767 bytes (115 words) - 22:32, 25 November 2015
• Manchester carry-chain adder
  ...of the chain results in a delay that is quadratic with the number of bits. Transistor sizing was performed to improve performance. The details are elaborated on ...s with the nubmer of stages (the critical path involves a series propagate transistor for each bit); so the delay will grow like n2.The worst case delay depends
  2 KB (421 words) - 23:00, 8 December 2015
• microcontroller
  ...transistor density]] and lower manufacturing costs than [[bipolar junction transistor|bipolar]] chips. MOS chips further increased in complexity at a rate predic ...chip in 1971. It was developed by [[Federico Faggin]], using his [[silicon-gate]] MOS technology, along with [[Intel]] engineers [[Marcian Hoff]] and [[Sta
  11 KB (1,575 words) - 20:44, 6 September 2024
• technology node
  ...referred to a number of different features of a transistor including the [[gate length]] as well as M1 half-pitch. Most recently, due to various marketing ...on of chips made in a particular technology. It does not correspond to any gate length or half pitch. Nevertheless, the name convention has stuck and it's
  13 KB (1,897 words) - 17:05, 5 October 2025
• 28 nm lithography process
  | process 1 transistor = Planar | process 1 gate len = 24 nm
  6 KB (711 words) - 17:01, 26 March 2019
• 32 nm lithography process
  | Contacted <br>Gate || 112.5 nm || 35 nm || -- | process 1 transistor = Planar
  10 KB (1,107 words) - 21:10, 19 March 2025
• 14 nm lithography process
  ...name for a generation of a certain size and its technology, as opposed to gate length or half pitch. [[File:intel 14nm gate.png|left|250px]]
  18 KB (2,283 words) - 20:34, 19 March 2025
• 45 nm lithography process
  ...Fab 28}} in Israel. Intel's 45 nm process is the first time high-k + metal gate transistors was used in high-volume manufacturing process. | Contacted <br>Gate || 180 nm || 60 nm || --
  5 KB (610 words) - 21:39, 19 March 2025
• intel/microarchitectures/bonnell
  ...is the first high-volume manufacturing process to introduce High-k + metal gate transistors. [[File:intel 45nm transistor.png|215px|left]]
  38 KB (5,468 words) - 08:27, 18 May 2025

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